TMS320C6A8167 Datasheet, PDF (138/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
Table 7-3. Timing Requirements for Reset (continued)
(see Figure 7-2 and Figure 7-3)
NO.
MIN
3 t_h(CONFIG)
Hold time, boot and configuration pins valid after POR high or RESET
0
high ⁽²⁾
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MAX UNIT
ns
Table 7-4. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 7-2)
NO.
t_w(RSTL)
4 t_{d(RSTL_IORST)}
5 t_{d(RSTL_IOFUNC)}
PARAMETER
Pulse width, RESET low
Delay time, RESET falling to all IO entering their reset state
Delay time, RESET rising to IO exiting their reset state
MIN
10C ⁽¹⁾
0
0
MAX
14
14
UNIT
ns
ns
ns
(1) C = 1/DEV_CLKIN clock frequency, in ns.
DEV_CLKIN
Power
Supplies
Ramping
Clock Source Stable
Power Supplies Stable
1
POR
RESET
BTMODE[4:0]
5
2
3
Hi-Z
Config
5
Other I/O Pins^(A)
RESET STATE
A. For more detailed information on the reset state of each pin, see Section 7.2.16, Pin Behaviors at Reset. For the
IPU/IPD settings during reset, see Section 3.2, Terminal Functions.
Figure 7-2. Power-Up Timing
138 Power, Reset, Clocking, and Interrupts
Copyright © 2010, Texas Instruments Incorporated
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