TMS320C6A8167 Datasheet, PDF (248/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
www.ti.com
8.17.1.2.2 Compatible JEDEC DDR2 Devices
Table 8-66 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 8-66. Compatible JEDEC DDR2 Devices
NO.
PARAMETER
1 JEDEC DDR2 device speed grade⁽¹⁾
MIN
DDR2-800
MAX UNIT
2 JEDEC DDR2 device bit width
3 JEDEC DDR2 device count⁽²⁾
4 JEDEC DDR2 device ball count⁽³⁾
x16
x16 Bits
1
2 Devices
84
92 Balls
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.
(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball
DDR2 devices are the same.
8.17.1.2.3 PCB Stackup
The minimum stackup required for routing the C6A816x device is a six-layer stack as shown in
Table 8-67. Additional layers may be added to the PCB stack up to accommodate other circuitry or to
reduce the size of the PCB footprint.
LAYER
1
2
3
4
5
6
Table 8-67. Minimum PCB Stack Up
TYPE
Signal
Plane
Plane
Signal
Plane
Signal
DESCRIPTION
Top routing mostly horizontal
Ground
Power
Internal routing
Ground
Bottom routing mostly vertical
248 Peripheral Information and Timings
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