AM1705 Datasheet, PDF (66/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657 – FEBRUARY 2010
www.ti.com
6.12.1 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• Supports 8, 9, 10 or 11 column address bits
• Supports up to 13 row address bits
• Supports 1, 2 or 4 internal banks
Table 6-21 shows the supported SDRAM configurations for EMIFB.
Table 6-21. EMIFB Supported SDRAM Configurations⁽¹⁾
SDRAM
Memory
Data Bus
Width
(bits)
Number of EMIFB Data
Memories Bus Size
Rows
Columns
Banks
Total Memory
(Mbits)
Total Memory
(Mbytes)
Memory
Density
(Mbits)
2
32
13
8
1
64
8
32
2
32
13
8
2
128
16
64
2
32
13
8
4
256
32
128
2
32
13
9
1
128
16
64
2
32
13
9
2
256
32
128
2
32
13
9
4
16
2
32
13
10
1
512
64
256
256
32
128
2
32
13
10
2
512
64
256
2
32
13
10
4
1024
128
512
2
32
13
11
1
512
64
256
2
32
13
11
2
1024
128
512
2
32
13
11
4
2048
256
1024
(1) The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 6-17 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. Figure 6-18
shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 6-22,
as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 6-22, page size/column size (not indicated in the
table) is varied to get the required addressability range.
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
SDRAM
2M x 16 x 4
CE
Bank
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 6-17. EMIFB to 2M × 16 × 4 bank SDRAM Interface
66
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Link(s): AM1705
Copyright © 2010, Texas Instruments Incorporated