AM1705 Datasheet, PDF (44/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657 – FEBRUARY 2010
OSCIN
CLKMODE
Square
Wave
1
Crystal 0
Pre-Div
PLL
PLLM
PLLEN
Post-Div
1
0
PLLDIV1 (/1)
PLLDIV2 (/2)
PLLDIV3 (/3)
PLLDIV4 (/4)
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SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
PLLDIV5 (/3)
PLLDIV7 (/6)
SYSCLK5
SYSCLK7
AUXCLK
DIV4.5
0
EMIFA
Internal
1
Clock
Source
CFGCHIP3[EMA_CLKSRC]
DIV4.5
1
EMIFB
Internal
Clock
0
Source
Figure 6-9. PLL Topology
CFGCHIP3[EMB_CLKSRC]
Table 6-5. Allowed PLL Operating Conditions
No.
PARAMETER
1
PLLRST: Assertion time during
initialization
Default
Value
N/A
MIN
1000
MAX
N/A
UNIT
ns
Lock time: The time that the application
2
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
N/A
PREDIV, PLLM, or OSCIN
3
PREDIV
/1
4
PLL input frequency
( PLLREF)
5
PLL multiplier values (PLLM) ⁽¹⁾
x20
6
PLL output frequency. ( PLLOUT )
N/A
7
POSTDIV
/1
Max PLL Lock Time = ^{2000 N}
m
N/A
where N = Pre-Divider Ratio
M = PLL Multiplier
/1
/32
12
50
x4
x32
400
600 ⁽²⁾
/2 ⁽²⁾
/32
OSCIN
cycles
(1)
ns
MHz
MHz
ns
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed 300 MHz. The Post Divider and SYSCLK divider values must be
chosen such that the CPU clocks do not exceed 300 MHz.
(2) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
44
Peripheral Information and Electrical Specifications
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