THS8083A95 Datasheet, PDF (51/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

5.4.9.2 Closed Loop
PARAMETER
TEST CONDITIONS MIN
TYP
MAX UNIT
f(HS)
t(acq)
t(JCS)
HS locking range
Lock-in time
Short-term jitter
See Note 16
15
100 kHz
5
ms
975 (p−p) 1500 (p−p)
260 (rms) 475 (rms)
ps
t(JCL) Long-term jitter
See Note 16
1025 (p−p) 1500 (p−p)
265 (rms) 485 (rms)
ps
NOTE 16: PLL characterization:
• Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (within the same video line) of
the clock rising edge. This is measured visually by capturing the clock and displaying it on a digital scope with a persistency of one
video line. Numerically, the time instants of the rising edges, at a defined voltage level, of a number of clock cycles (N = 800) are
captured at a high sampling rate. The average clock time period is calculated from these time instants. The deviation between
each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value
along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
• Long term jitter in closed loop is defined as the variation over one video frame of the Nth clock rising edge on each line. This is
measured by capturing the time instant at a defined level on the rising edge of the Nth clock after HS is reached on each line. The
calculation uses the same principle used with short term jitter, but now takes one sample on every line and N = 800 lines.
5.4.10 Typical Plots (25°C and Measured for Standard VESA Graphics Formats)
1600
1500
POWER
vs
FREQUENCY
VCC = 3.3 V
CURRENT
vs
FREQUENCY
350
Total Analog
300
1400
1300
1200
250
AVDD_CH1+AVDD_CH2_3
200
150
DVDD_PLL
AVDD_REF
100
Total Digital
DVDD
1100
1000
0
50
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
AVDD_PLL
0
0 10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
Figure 5−2. Power Consumption
5−7