THS8083A95 Datasheet, PDF (25/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

3 Register Definition
3.1 I²C Protocol
The THS8083A95 is a slave I²C device that supports both write and read. As shown in Table 3−1, I²C Register Map,
there are some status control registers that can only be read.
The device can support FAST I²C mode (SCL up to 400 kHz) when the DTO clock is running at over 25 MHz; at lower
DTO frequencies, only NORMAL I²C mode (SCL up to 100 kHz) is supported.
To discriminate between write and read operations, the device is addressed at separate device addresses. There is
an automatic internal subaddress increment counter to efficiently write/read multiple bytes in the register map during
one write/read operation. Furthermore, bit 1 of the I²C device address is dependent upon the I2CA pin setting, as
follows:
If address selecting pin I2CA = 0, then
Write address is 40 hex (01000000)
Read address is 41 hex (01000001)
If address selecting pin I2CA = 1, then
Write address is 42 hex (01000010)
Read address is 43 hex (01000011)
3.1.1 Write Format
S Slave address(w) A Subaddress A Data0 A
……
S
Slave address(w)
A
Start condition
0100000 (0x40) if I2CA=0 / 01000010 (0x42) if I2CA=1
Acknowledge. It is generated by THS8083A95.
Subaddress
Data0
Data(N−1)
P
Subaddress of first register to write, length: 1 byte
First byte of data
Nth byte of data
Stop condition
Data(N−1) A P
3−1