THS8083A95 Datasheet, PDF (43/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

4.3 Timing Diagram—48-Bit Interleaved Mode
This mode allows a double-pixel width output interface with one sampling clock period time offset between buses A
and B. The DATACLK1 output is at half of the sampling clock frequency. Data on output bus A precedes data on output
bus B.
ADCCLK2
DATACLK
CH1_OUTA[7..0]
CH1_OUTB[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
pix 01 pix 02
7 ADCCLK2 Cycles Latency
tPLH(OE)
Last Samples From Previous Line
Last Samples From Previous Line
Last Samples From Previous Line
Last Samples From Previous Line
Last Samples From Previous Line
Last Samples From Previous Line
tPHL(OE)
tsu(OUT)
th(OUT)
01
03
tsu(OUT)
th(OUT)
02
04
01
03
02
04
01
03
02
04
7 ADCCLK2
Cycles Latency
DHS
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
tsu(DHS)
th(DHS)
<DHS_MODE> = 1 −> Width
Equal to Width of HS Input
<DHS_MODE> = 0 −> DHS
Width is 1 ADCCLK2 Period
4−3