THS8083A95 Datasheet, PDF (49/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

5.4.5.2 Dynamic Performance^†
PARAMETER
TEST CONDITIONS
ADC_INTREF
MIN TYP MAX UNIT
Effective number of bits, ENOB (from SNR)
fI = 20 MHz
6.5
Bits
Signal-to-total ratio without distortion, SNR
fI = 20 MHz
42
dB
Total harmonic distortion, THD
fI = 1 MHz
−47
dB
Spurious free dynamic range, SFDR
fI = 1 MHz
51
dB
Analog input full-power bandwidth, BW
(see Note 11)
500
MHz
† _{Based on analog input voltage of 1 dB FS referenced to the full-scale input range and a clock signal with 50% duty cycle}
NOTE 11: Analog input bandwidth—The analog input bandwidth is defined as the maximum frequency of the input sine that can be applied to the
device for which a 3 dB attenuation is observed in the reconstructed signal.
5.4.5.3 Clamp
PARAMETER
TEST CONDITIONS
ADC_INTREF
MIN TYP MAX UNIT
Clamp code adjustment range
See Note 12
100
138 LSB
Clamp acquisition time at input dc level change
Input level changed by ^{Within 10% of final value}
100 mV
Within 1 LSB of final value
1
ms
2.4
ms
Clamp acquisition time, clamp code change
Clamp changed from
minimum to maximum
Within 1 LSB
500 1000 ns
Clamp droop error
Droop between 2 clamps at 15 kHz line rate
0.5 1.6 LSB
NOTE 12: Clamp code adjustment range—A dc-input signal is applied to the device. The clamp code is changed from minimum to maximum
setting. The corresponding change in the ADC output code is defined as the clamp code adjustment range.
5.4.6 Coarse PGA
Full-scale adjustment range
Accuracy
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
0.4
1.2 V
±6
LSB
5.4.7 Fine PGA
PARAMETER
Full-scale adjustment range
TEST CONDITIONS
MIN TYP MAX UNIT
−4
8 LSB
5−5