THS8083A95 Datasheet, PDF(21/66 Page) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

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THS8083A95 Datasheet, PDF (21/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

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PFD_FREEZE

DTO_DIS

VCOCLK

(From Analog PLL)

HS_POL HS_MS

POL

Noise

Gate

HS_WIDTH

LD_THRESH

DISABLE_

PFD

SELCLK

MUX

Compensated in Output

Formatter for Pipeline

Data Delay. Then Output

on Terminal DHS With

Polarity Determined by

<DHS_POL>.

DHS_MODE

DIV2

Phase-

Frequency

Detector

PROG.

LOOP

FILTER

DTO DIV

3P 3

GAIN_N GAIN_P

NOM_INC

Phase PLLCLK

Selector

MUX

PHASESEL

SEL_ADCCLK

INV2

Lock

Detection

8 Hysteresis

Programmable

Divider

TERM_CNT

to ADC

DIV3

INV3

ADCCLK2

ADCCLK1

(see NOTE)

DTOCLK3

LOCK

NOTE: ADCCLK1 is used by the output formatter to generate the DATACLK1 output.

EXT_ADCCLK

Figure 2â6. Digital PLL

The device provides three clock outputs. One output signal, DATACLK1, is derived from the ADC clock output. It is

actually equal to the sampling clock, but compensated in phase so that its rising edge always corresponds to the

center valid region of the output data. Output data timing (setup/hold) is specified with respect to this rising edge.

Therefore, DATACLK1 is typically used for clocking the THS8083A95âs output data. The frequency of DATACLK1 is

either equal to, or one half the sampling clock, depending on the operation mode of the output formatter. When the

THS8083A95 is clocked with an external sampling clock, this external clock is used as the source to generate

DATACLK1 in the output formatter.

The second clock output, ADCCLK2, is equal to the ADC sampling clock, but can optionally be divided by 2 and

inverted.

The third clock output, DTOCLK3, is always derived from the PLL output clock, irrespective of the use of an external

sampling clock on EXT_ADCCLK. So, when operating with an external sampling clock, the DTOCLK3 output can be

used to generate a second, possibly asynchronous, clock signal in either open or closed loop operation locked to a

reference HS input. Also, DTOCLK3 can be optionally divided by 2 and inverted.

The divide and invert functions are implemented to enable a two-part master/slave operation in case sampling speeds

higher than 95 MSPS are required. In this case, the master uses its PLL to generate a line-locked clock, and its inverse

is used by the second slave device as an external sampling clock.

2â7

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