THS8083A95 Datasheet, PDF (34/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

3.2.18 Register Name: HS_COUNT_1
MSB
X
X
X
X
HS_COUNT[11..8]:
See register HS_COUNT_0
Default: (changed during operation)
Subaddress: 11 (R)
HS_COUNT11 HS_COUNT10 HS_COUNT9
LSB
HS_COUNT8
3.2.19 Register Name: VS_COUNT_0
Subaddress: 12 (R)
MSB
VS_COUNT7 VS_COUNT6 VS_COUNT5 VS_COUNT4
VS_COUNT3 VS_COUNT2 VS_COUNT1
LSB
VS_COUNT0
VS_COUNT[7..0]:
VS_COUNT[11..0] holds the last vertical sync period number (i.e., the number of line periods between the
last two VS occurrences). The device updates the value at each active edge of VS. Internal arbitration logic
avoids potential read errors between the register contents and the asynchronous I²C bus. This value can be
read by the microcontroller to derive the frame rate of the incoming video/graphics format.
Default: (changed during operation)
3.2.20 Register Name: VS_COUNT_1
MSB
X
X
X
X
VS_COUNT[11..8]
See register VS_COUNT0
Default: (changed during operation)
Subaddress: 13 (R)
VS_COUNT11 VS_COUNT10 VS_COUNT9
LSB
VS_COUNT8
3.2.21 Register Name: DTO_INC_0
Subaddress: 14 (R)
MSB
DTO_INC7
DTO_INC6 DTO_INC5
DTO_INC4 DTO_INC3
DTO_INC2
DTO_INC1
LSB
DTO_INC0
DTO_INC[7..0]
DTO_INC[32..0] stores the current value of the DTO increment. This can be read by the microcontroller to
derive the actual pixel clock frequency.
Default: (changed during operation)
3.2.22 Register Name: DTO_INC_1
MSB
DTO_INC15
DTO_INC14 DTO_INC13
DTO_INC12
DTO_INC[15..8]:
See register DTO_INC_0
Default: (changed during operation)
DTO_INC11
DTO_INC10
Subaddress: 15 (R)
DTO_INC9
LSB
DTO_INC8
3−10