THS8083A95 Datasheet, PDF (32/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

3.2.13 Register Name: VS_WIDTH
Subaddress: 0C (R/W)
MSB
VS_WIDTH7
VS_WIDTH6
VS_WIDTH5
VS_WIDTH4 VS_WIDTH3 VS_WIDTH2
VS_WIDTH1
LSB
VS_WIDTH0
VS_WIDTH[7..0]:
Sets the width in lines for VS detection. If the width of the incoming VS is less than this number, it is ignored.
The width in lines of an incoming VS is incremented each time a valid HS is detected during a VS active.
Therefore, the programmed width is the minimum number of horizontal syncs spanned by the active
duration of VS.
Default: 0x00
3.2.14 Register Name: SYNC_CTRL
Subaddress: 0D (R/W)
MSB
X
LSB
X
X
X
HS_POL
HS_MS
VS_POL
VS_MS
HS_POL:
Controls the polarity of the incoming HS
0 = positive polarity (default)
1 = negative polarity
HS_MS:
Controls the mux selection for activating the noise filter on incoming HS
0 = noise filter disabled (default)
1 = noise filter enabled
VS_POL:
Controls the polarity of the incoming VS
0 = positive polarity (default)
1 = negative polarity
VS_MS:
Controls the mux selection for activating the noise filter on incoming VS
0 = noise filter disabled (default)
1 = noise filter enabled
3.2.15 Register Name: LD_THRES
Subaddress: 0E (R/W)
MSB
LD_THRES7 LD_THRES6
LD_THRES5 LD_THRES4 LD_THRES3
LSB
LD_THRES2 LD_THRES1 LD_THRES0
LD_THRES[7..0]:
Sets hysteresis for PLL lock-detection output.
An internal counter counts the number of subsequent lines onto which lock is found, as follows: for each line
(HS) on which the PFD finds that the PLL is locked, the counter is incremented by 1. The counter clips at 255
maximum. For each line (HS) that the PLL is not locked to, the counter is decremented by 8. This counter
starts from 0.
Lock is signaled externally (via the LOCK_DETECT output) when this internal counter holds a value higher
than <LD_THRESHOLD>. Unlock is signaled externally when this internal counter holds a value less than
or equal to <LD_THRESHOLD>. So, a value of 255 will never assert the lock signal, although the PLL might
be locked internally.
NOTE: the higher this value is set, the more critical the PFD will be to signal lock. Therefore, this value must
be lower for high jitter HS inputs than for high quality sources.
Default: 0x10 = 16
3−8