THS8083A95 Datasheet, PDF (29/66 Pages) Texas Instruments – TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS

3.2 Register Description
Register values after reset/at power up/after power down mode: The default value with each register shows the
start-up condition after general chip reset. The register state after power up is undefined i.e., the device requires a
reset after power up (RESET low) to put all registers in their default states. The value of these registers is preserved
in all power-down modes (i.e. after power down the register values are identical as when entering power down); they
do not return to their default values under this condition. In order for the device to reset correctly, a master clock signal
needs to be applied during reset from either a clock signal on XTL1−MCLK or a crystal connected between
XTL1−MCLK and XTL2. The reset signal needs to be at least 5 clock cycles wide.
Default values: The default values for this device are set for XGA@78.75 MHz.
3.2.1 Register Name: TERM_CNT_0
Subaddress: 00 (R/W)
MSB
TERM_CNT7 TERM_CNT6 TERM_CNT5 TERM_CNT4 TERM_CNT3 TERM_CNT2 TERM_CNT1
LSB
TERM_CNT0
TERM_CNT[7..0]:
TERM_CNT[11..0] sets the number of pixels per line. Controls the digital PLL feedback divider.
Default: 0x20
3.2.2 Register Name: TERM_CNT_1
Subaddress: 01 (R/W)
MSB
LSB
X
X
X
X
TERM_CNT11 TERM_CNT10 TERM_CNT9 TERM_CNT8
TERM_CNT[11..8]:
See register TERM_CNT_0.
Default: 0x5
Default TERM_CNT: 0x520 = 1312 pixels/line (XGA@75 Hz)
3.2.3 Register Name: NOM_INC_0
MSB
NOM_INC7
NOM_INC6 NOM_INC5 NOM_INC4
NOM_INC3
NOM_INC[7..0]:
NOM_INC[32..27]: integer part of DTO increment value
NOM_INC[26..0] : fractional part of DTO increment value
(See Appendix A for how to calculate the increment)
Default: 0x16
NOM_INC2
Subaddress: 02 (R/W)
NOM_INC1
LSB
NOM_INC0
3.2.4 Register Name: NOM_INC_1
MSB
NOM_INC15
NOM_INC14 NOM_INC13 NOM_INC12
NOM_INC[15..8]:
See register NOM_INC_0.
Default: 0x8A
NOM_INC11
NOM_INC10
Subaddress: 03 (R/W)
NOM_INC9
LSB
NOM_INC8
3−5