TLK2541 Datasheet, PDF(5/26 Page) Texas Instruments

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TLK2541

www.ti.com...................................................................................................................................................... SLLS779B â JANUARY 2008 â REVISED APRIL 2008

TERMINAL

NAME

NO.

RXRATE

PRBSPASS

/FIFO_ERR

PRE

CTRL0

CTRL1

RXCODE

SYNCEN

TERMINAL FUNCTIONS (continued)

TYPE

DESCRIPTION

Input (w/Pull-up)

Output

(low on power-up)

Input (w/pull down)

Input (w/Pull-up)

Receive Rate Select. When pulled high or left unconnected, the receive path expects to

operate at a data rate of approximately 20 times REFCLK. This provides a data rate range

of 2.0 to 2.6 Gbps. In this mode, the width of the receive parallel bus is 2 Bytes, either 20

bit coded data or 16 bit date plus two K-status bits of un-coded data.

When pulled low, the receive path expects to operate at a data rate of approximately 10

times REFCLK. This provides a data rate range of 1.0 to 1.3 Gbps. In this mode, the width

of the receive parallel bus is 1 Byte, either 10 bit coded data or 8 bit date plus one K-status

bit of uncoded data.

PRBS PASS Output. When PRBSEN is enabled, this pin reflects the result of the on-chip

PRBS verifier. When the PRBS verifier is detects that the de-serialized data stream

matches the PRBS data pattern then this output goes high. If the PRBS verifier detects

one or more bits in a received word that do not match the PRBS pattern then this output

goes low for that clock cycle.

When PRBSEN is enabled, the PRBSPASS output my be latched or unlatched. If the

PRBSPASS is not latched, then the PRBSPASS output will go low for only the clock cycle

in which there is an error detected in the PRBS pattern. If the PRBSPASS is latched, then

the PRBSPASS will go low and remain low when an error is detected. While PRBSEN is

active, SYNCEN controls whether the PRBSPASS is latched or not latched. When

SYNCEN is high, the PRBSPASS is latched. When SYNCEN is low, the PRBSPASS is not

latched. When used in latched mode, toggling SYNCEN is used to clear a latched

PRBSPASS output.

When PRBSEN is not enabled, then this pin becomes FIFO_ERR. FIFO_ERR will go

active whenever the internal transmit FIFO overflows or underflows and remain active until

the FIFO reinitializes itself, which typically takes a few clock cycles. FIFO_ERR should

never go active unless there is excessive wander on the TXCLK relative to REFCLK, or

there is a frequency mismatch between the TX_CLK and REFCLK clock domains. The

TX_CLK may accept as much as Â±1 byte of phase wander relative to REFCLK, but the

TX_CLK must be frequency locked to REFCLK and have 0-ppm frequency mismatch

between TX_CLK and REFCLK. The transmit FIFO automatically reinitializes itself upon

power-up reset or upon detection of an overflow or underflow.

Pre-emphasis Control. Selects the amount of pre-emphasis to be added to the

high-speed serial output drivers. Left low or unconnected, 5% pre-emphasis is added.

Pulled high, 20% pre-emphasis is added.

Mode Select. These control pins control the format of the data on the transmit parallel bus.

The parallel data may be in the form of 10-bit coded 8B/10B data in which case the data

bypasses the on-chip 8b/10b encode logic on the TLK2541. The data may also be

un-coded data in the form of 8 bits data plus a K-control bit in which case the data path

makes use of the on-chip 8b/10b encode logic on the TLK2541.

When the on-chip 8b/10b encode logic is utilized, there are additional modes available

where the TLK2541 can properly maintain the Gigabit Ethernet IEEE802.3 IDLE patterns

or properly maintain the ANSI FibreChannel EOF End Of Frame patterns.

CTRL0 = 0, CTRL1 = 0: Raw 10 bit or 20 bit coded data

CTRL0 = 0, CTRL1 = 1: 8 bit or 16 bit un-coded data GigEther mode

CTRL0 = 1, CTRL1 = 0: 8 bit or 16 bit un-coded data FibreChannel Mode

CTRL0 = 1, CTRL1 = 1: 8 bit or 16 bit un-coded data

RXCODE. This control pin controls the format of the data on the receive parallel bus.

When RXCODE is low, the parallel data will be in the form of 10-bit coded 8B/10B data in

which case the data bypasses the on-chip 8b/10b decode logic on the TLK2541. When

RXCODE is high, the data will be un-coded data in the form of 8 bits data plus a K-status

bit in which case the data path makes use of the on-chip 8b/10b decoder.

SYNCEN Enable. When high, this pin enables the coma detect logic to byte-align the

receiver to the location of the comma.

Product Folder Link(s) :TLK2541

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