TLK2541 Datasheet, PDF(11/26 Page) Texas Instruments

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TLK2541

www.ti.com...................................................................................................................................................... SLLS779B â JANUARY 2008 â REVISED APRIL 2008

DETAILED DESCRIPTION

TRANSMIT INTERFACE

The TLK2541 offers four modes of operation for the transmit data path. The TLK2541 can operate as a 10 bit

SERDES at 10 times the rate of REFCLK or as a 20 bit SERDES at 20 times the rate of REFCLK. At either rate,

the data may be serialized exactly as presented on the parallel bus or it may be coded into 8B/10B data codes

by way on an integrated 8B/10B encoder.

TRANSMIT DATA BUS

At full data rate, The transmitter portion registers valid incoming 20-bit wide data (TXD[0:19]) on the rising edge

of the TX_CLK. The data is then serialized and transmitted sequentially over the differential high-speed I/O

channel. The clock multiplier multiplies the reference clock (REFCLK) by a factor of 10 times, creating a bit clock.

This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising and

falling edges of the internal bit clock, providing a serial data rate that is 20 times the input clock. Data is

transmitted LSB TXD[0] first. If the 8B/10B encoder is enabled, the data is latched as 16 bits of data plus two bits

of control. The lower order byte is latched on TXD[0:7] and the higher order byte is latched on TXD[8:15]. Bit

TXD[16] controls whether the lower order byte is coded as a Dx.y data word or a Kx.y control word. Bit TXD[17]

controls whether the higher order byte is coded as a Dx.y data word or a Kx.y control word. Bits TXD[18] and

TXD[19] are ignored.

At half data rate, The transmitter portion registers valid incoming 10-bit wide data (TXD[0:9]) on the rising edge of

the TX_CLK. The data is then serialized and transmitted sequentially over the differential high-speed I/O

channel. Bits TXD[10:19] are ignored. The clock multiplier multiplies the reference clock (REFCLK) by a factor of

5 times, creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data

on both the rising and falling edges of the bit clock, providing a serial data rate that is 10 times the input clock.

Data is transmitted LSB (TXD[0]) first. If the 8B/10B encoder is enabled, the data is latched as 8 bits of data plus

one bit of control. The lower order byte is latched on TXD[0:7]. Bit TXD[16] controls whether the lower order byte

is coded as a Dx.y data word or a Kx.y control word. Bits TXD[8:15] and TXD[17:19] are ignored. The data and

clock signals must be properly aligned as shown in Figure 5. Detailed timing information can be found in the

electrical characteristics table.

TX_CLK

TXD[0-19]

Figure 5. Transmit Timing Waveform

Transmit Rate Select

The TLK2541 has two ranges of operation. The TLK2541 may be used to serialize 20 bits of data at a data rate

of 20 times the reference clock, or the TLK2541 may be used to serialize 10 bits of data at a rate of 10 times the

reference clock. In either case, the reference clock must be in the range of 100 to 130 MHz, allowing the

TLK2541 to be used as a 10-bit serializer at a rate of 1 to 1.3 Gbps or as a 20-bit serializer at a rate of 2 to 2.6

Gbps. The control pin TXRATE selects the range of operation for the TLK2541 serializer.

When TXRATE is low, the TLK2541 serializes the 10 bit data on TXD[0:9] at a rate of 10 times the reference

clock. Bits TXD[10:19] is ignored. If the 8B/10B encoder is enabled, then bits TXD[0:7] is encoded into a 10 bit

code word and bit TXD[16] controls whether the code is a Dx.y code if TXD[16] is low or a Kx.y code if TXD[16]

is high. Bit TXD[9] is ignored.

Product Folder Link(s) :TLK2541

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