TLK2541 Datasheet, PDF (12/26 Pages) Texas Instruments – 1 TO 2.6 GBPS TRANSCEIVER

TLK2541
SLLS779B – JANUARY 2008 – REVISED APRIL 2008...................................................................................................................................................... www.ti.com
When TXRATE is high, the TLK2541 serializes the 20 bit data on TXD[0:19] at a rate of 20 times the reference
clock. Bit TXD[0] is the first bit serialized. If the 8B/10B encoders are enabled, then bits TXD[0:7] is encoded into
the lower order 10 bit code word and bits TXD[8:15] is encoded into the higher order 10 bit code word. The lower
order code word is serialized first. Bit TXD[16] controls whether the lower order code is a Dx.y code if TXD[16] is
low or a Kx.y code if TXD[16] is high. Bit TXD[17] controls whether the higher order code is a Dx.y code if
TXD[17] is low or a Kx.y code if TXD[17] is high. Bits TXD[18] and TXD[19] is ignored.
When TXRATE is high, it is expected (but not required) that a K28.5 code such as that used in a Gigabit
Ethernet IDLE or a FibreChannel ordered set be present on the lower order byte. This is because at the higher
data rate the parallel bus is two bytes wide, and if the receiver is also a TLK2541 with a two-byte wide parallel
bus then the receiver must determine which byte to output on the lower order byte of the receive parallel bus.
The TLK2541 receiver expects the K28.5 code to be present on the lower order byte and thus the receiver
chooses a 20 bit deserialization boundary such that the K28.5 is present on the lower order byte.
TRANSMISSION LATENCY
The data transmission latency of the TLK2541 is defined as the delay from the initial 20-bit word load to the
serial transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies.
The minimum transmit latency t_{d(Tx latency)} is 50 bit times; the maximum is 86 bit times when 8b/10b coding is off.
The minimum transmit latency t_{d(Tx latency)} is 70 bit times; the maximum is 106 bit times when 8b/10b coding is on.
Figure 6 illustrates the timing relationship between the transmit data bus, the TX_CLK, and the serial transmit
terminals.
TXD[0-19]
Parallel Word to Transmit
TX_CLK
Figure 6. Transmission Latency
Optional 8-BIT/10-BIT ENCODER
All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving
PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc
balance by keeping the number of ones and zeros the same. This provides good transition density for clock
recovery and improves error checking. The TLK2541 uses the 8-bit/10-bit encoding algorithm that is used by
fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2541 internally encodes and
decodes the data such that the user reads and writes actual 16-bit data.
The 8-bit/10-bit encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve its
transmission characteristics. Since the TLK2541 is a 16-bit wide interface, the data is split into two 8-bit wide
bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependent upon two additional
input signals are presented on pins TXD[16] and TXD[17]. See Table 3.
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