TLK2541 Datasheet, PDF(15/26 Page) Texas Instruments

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TLK2541

www.ti.com...................................................................................................................................................... SLLS779B â JANUARY 2008 â REVISED APRIL 2008

in the center of the output data word. The first data bit received is output on RXD[0]. If the 8B/10B encoder is

enabled, the data is output as 8 bits of data plus one bit of status. The lower order byte is output on RXD[0:7]. Bit

RXD[16] indicates whether the lower order byte was decoded as a Dx.y data word or a Kx.y control word. Bits

RXD[8:15] and RXD[17:19] and are high impedance The data and clock signals are aligned as shown in

Figure 8. Detailed timing information can be found in the switching characteristics table.

RX_CLK

RXD[0-19]

Figure 8. Receive Timing Waveform

Data Reception Latency

The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output

in the aligned parallel word. The receive latency is fixed once the link is established. However, due to silicon

process variations and implementation variables such as supply voltage and temperature, the exact delay varies.

The minimum receive latency td(Rx latency) is 81 bit times; the maximum is 93 bit times for full rate operation. The

minimum receive latency td(Rx latency) is 69 bit times; the maximum is 81 bit times for half rate operation. Figure 9

illustrates the timing relationship between the serial receive terminals, the recovered word clock (RX_CLK), and

the receive data bus.

RXD[0-19]

Decoded Parallel Word

RX_CLK

Figure 9. Receiver Latency

Serial-to-Parallel

Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the

data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The

recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel

shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders

where the data is then synchronized to the incoming data stream word boundary by detection of the comma

8-bit/10-bit synchronization pattern.

Comma Detect and Optional 8-Bit/10-Bit Decoding

The TLK2541 has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded

data (half of the 20-bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte

synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial

converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.

When the serial data is received and converted to parallel format again, a method is needed to recognize the

byte boundary. This is accomplished through the use of a synchronization pattern. This is a unique pattern of 1's

and 0's that either cannot occur as part of valid data, or is a pattern that repeats at defined intervals. The

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