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TLK2541 Datasheet, PDF (14/26 Pages) Texas Instruments – 1 TO 2.6 GBPS TRANSCEIVER
TLK2541
SLLS779B – JANUARY 2008 – REVISED APRIL 2008...................................................................................................................................................... www.ti.com
PRBS Generator
The TLK2541 has a built-in 27-1 PRBS (pseudo random bit stream) function. When the PRBSEN terminal is
forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter
input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then
fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent
to a BERT (bit error rate tester), the receiver of another TLK2541, or looped back to the receive input. Since the
PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and
checked for errors by a BERT.
Parallel-to-Serial
The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit
encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the
internally generated bit clock, which is 10 times the REFCLK input frequency. The LSB (TXD[0]) is transmitted
first.
High-Speed Data Output
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω
impedance environment. The magnitude of the differential pair signal swing is compatible with pseudo emitter
coupled logic (PECL) levels when ac-coupled. The line can be directly-coupled or ac-coupled. See Figure 11 and
Figure 12 for termination details. The outputs also provide preemphasis to compensate for ac loss when driving a
cable or PCB backplane trace over a long distance (see Figure 7). The level of pre-emphasis is controlled by
PRE as shown in Table 4.
Table 4. Programmable Pre-emphasis
PRE
0
1
PRE-EMPHASIS LEVEL(%)
VOD(P), VOD(D) (1)
5%
20%
Figure 7. Output Voltage Under Pre-emphasis
(|VTXP–VTXN|)
(1) VOD(p) : Voltage swing when there is a transition in the data
stream
VOD(d): Voltage swing when there is no transition in the data
stream.
RECEIVE INTERFACE
The receiver portion of the TLK2541 accepts 8-bit/10-bit encoded differential serial data. The interpolator and
clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to
retime the input data stream. The recovered clock is divided down to output a receive word clock that is output
on RX_CLK. The parallel data is presented on the parallel output bus according to four modes of operation. The
TLK2541 can operate as a 10 bit SERDES at 10 times the rate of REFCLK or as a 20 bit SERDES at 20 times
the rate of REFCLK. At either rate, the data may be deserialized, byte aligned and output exactly as it is
captured from the serial inputs or it may be decoded into data bytes by way on an integrated 8B/10B decoder.
Receive Data Bus
At full data rate, the receiver portion locks to an incoming serial data stream and deserializes the data into 20-bit
wide data words and outputs them on RXD[0:19] along with the RX_CLK. RX_CLK is aligned with the rising edge
in the center of the output data word. The first data bit received is output on RXD[0]. If the 8B/10B decoder is
enabled, the data is output as 16 bits of data plus two bits of status. The lower order byte is output on RXD[0:7]
and the higher order byte is output on RXD[8:15]. Bit RXD[16] indicates whether the lower order byte was
decoded as a Dx.y data word or a Kx.y control word. Bit RXD[17] indicates whether the higher order byte was
decoded as a Dx.y data word or a Kx.y control word. Bits RXD[18] and RTXD[19] are high impedance.
At half data rate, the receiver portion locks to an incoming serial data stream and deserializes the data into 10-bit
wide data words and outputs them on RXD[0:9] along with the RX_CLK. RX_CLK is aligned with the rising edge
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