TLK2541 Datasheet, PDF (4/26 Pages) Texas Instruments – 1 TO 2.6 GBPS TRANSCEIVER

TLK2541
SLLS779B – JANUARY 2008 – REVISED APRIL 2008...................................................................................................................................................... www.ti.com
TERMINAL
NAME
NO.
DOUTTXP
72
DOUTTXN
71
DINRXP
67
DINRXN
66
TX_CLK
10
REFCLK
75
TXD0
78
TXD1
79
TXD2
1
TXD3
3
TXD4
4
TXD5
5
TXD6
6
TXD7
8
TXD8
9
TXD9
12
TXD10
13
TXD11
14
TXD12
16
TXD13
17
TXD14
18
TXD15
19
TXD16
21
TXD17
23
TXD18
24
TXD19
25
RXD0
63
RXD1
62
RXD2
61
RXD3
58
RXD4
57
RXD5
56
RXD6
55
RXD7
54
RXD8
51
RXD9
50
RXD10
49
RXD11
47
RXD12
46
RXD13
45
RXD14
44
RXD15
43
RXD16
39
RXD17
38
RXD18
37
RXD19
36
RX_CLK
52
TXRATE
77
TERMINAL FUNCTIONS
TYPE
Output
(Hi-Z power-up)
Input
Input
Input
Input
Output (Hi-Z on
power- up)
Output (low on
power-up)
Input (w/Pull-up)
DESCRIPTION
Serial Transmit Outputs. DOUTTXP and DOUTTXN are differential serial outputs that
interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of
10 or 20 times the TX_CLK value. DOUTTXP and DOUTTXN are put in a high impedance
state when LOOPEN is high and are active when LOOPEN is low. When Disabled or
during power-on-reset these pins are high impedance.
Serial Receive Inputs. DINRXP and DINRXN together are the differential serial input
interface from a copper or an optical I/F module.
Transmit Clock. TX_CLK is a continuous external input clock that synchronizes the
transmitter parallel interface signals TXD[0:19]. The frequency range of TX_CLK is 100
MHz to 130 MHz. The transmitter uses the rising edge of this clock to register the input
data (TXD) for serialization.
Reference Clock. REFCLK is a clean reference clock for input to the phase lock loop.
REFCLK must be the same frequency as TX_CLK.
Transmit Data Bus. These inputs carry the 20-bit parallel data output from a protocol
device to the transceiver for serialization and transmission. This 20-bit parallel data is
clocked into the transceiver on the rising edge of TX_CLK.
When the transmitter is operating at 20 times REFCLK rate, the full width of the transmit
parallel bus is latched on the rising edge of TX_CLK and serialized. When the transmitter
is operating at 10 times REFCLK rate, only the lower half of the transmit parallel bus is
latched and serialized.
When the on-chip encode/decode logic is bypassed, the full 20 bit data bus is serialized at
full data rate. At half data rate only bits TXD0 through TXD9 are serialized.
When the on-chip encode/decode logic is utilized, bits TXD[0:7] make up the lower order
data byte and bit TXD[16] becomes the K control bit for the lower order byte. Bits
TXD[8:15] make up the higher order byte and bit TXD[17] becomes the K control bit for the
higher order byte. Bits TXD[18] and TXD[19] are ignored. At full data rate both lower and
higher order bytes are latched, coded, and serialized. At half data rate, only the lower order
byte is latched, coded and serialized.
The lower order byte is always serialized first, and the lower order bit in a byte is always
serialized first.
Receive Data Bus. These outputs carry 20-bit parallel data output from the transceiver to
the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of
RX_CLK. These pins are high impedance during power-on reset.
When the receiver is operating at 20 times REFCLK rate, the full width of the receive
parallel bus is valid on the rising edge of RX_CLK. When the receiver is operating at 10
times REFCLK rate, only the lower half of the receive parallel bus is valid on the rising
edge of RX_CLK.
When the on-chip encode/decode logic is bypassed, raw coded data is presented on the
receive parallel bus. At full data rate, data is presented on bits RXD0 through RXD19. At
half data rate only bits RXD0 through RXD9 are valid
When the on-chip encode/decode logic is utilized, bits RXD[0:7] make up the lower order
data byte and bit RXD[16] becomes the K status bit for the lower order byte. Bits
RXD[8:15] make up the higher order byte and bit RXD[17] becomes the K status bit for the
higher order byte. Bits RXD[18] and RXD[19] are high impedance. At full data rate both
lower and higher order bytes are de-serialized, decoded and output. At half data rate, only
the lower order byte is de-serialized, decoded and output.
The first received byte is always output on the lower order byte, and the first bit to be
received is always presented in the lower order bit of a byte.
Recovered Clock. Output clock that is synchronized to RXD[0:19]. RX_CLK is the
recovered serial data rate clock divided by 10 or 20 depending on rate selection. RX_CLK
is low during power-on reset.
Transmit Rate Select. When pulled high or left unconnected, the transmit path operates at
a data rate of 20 times REFCLK. This provides a data rate range of 2.0 to 2.6 Gbps. In this
mode, the width of the transmit parallel bus is 2 Bytes, either 20 bit coded data or 16 bit
date plus two K-control bits for uncoded data. When pulled low, the transmit path operates
at a data rate of 10 times REFCLK. This provides a data rate range of 1.0 to 1.3 Gbps. In
this mode, the width of the transmit parallel bus is 1 Byte, either 10 bit coded data or 8 bit
date plus one K-control bit for uncoded data.
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