TLK2541 Datasheet, PDF (18/26 Pages) Texas Instruments – 1 TO 2.6 GBPS TRANSCEIVER

TLK2541
SLLS779B – JANUARY 2008 – REVISED APRIL 2008...................................................................................................................................................... www.ti.com
Reference Clock Input
The reference clock (REFCLK) is an external input clock that sets the rate of the transmitted serial data stream.
The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. In full
rate mode, the internal serialization bit clock is frequency-locked to the input clock and used to clock out the
serial transmit data on both its rising and falling edges, providing a serial data rate that is 20 times the input
clock.
Operating Frequency Range
The TLK2541 can operate at a serial data rate from 1.0 Gbps to 1.3 Gbps or 2.0 to 2.6 Gbps. To achieve these
serial rates, REFCLK must be within 100 MHz to 130 MHz. The frequency accuracy of REFCLK is expected to
be within 100 PPM of the desired rate. The transmit path data rate will be set by REFCLK and the receive path
data rate is expected to be within 200 PPM of the transmit path data rate.
Testability
The TLK2541 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled
so that a quiescent current test can be performed. The PRBS function allows for BIST (built-in self-test).
Loopback Testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling this
terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be
compared to the parallel input data for functional verification. (The external differential output is held in a high
impedance state during the loopback testing.)
Built-In Self-Test (BIST)
The TLK2541 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the PRBSPASS
terminal. The PRBS generation and verification can operate at either full rate or half rate, but both PRBS
generation and verification must be at the same rate or PRBSPASS will report an error condition.
Power-On Reset
Upon application of minimum valid power or upon application of a minimum toggling reference clock, the
TLK2541 generates a power-on reset. During the power-on reset the RXD[0:19] and serial output signal
terminals go to a high impedance state. The RX_CLK is held low. The length of the power-on reset cycle is
dependent upon the input frequency, but is less than 1 ms.
THERMAL INFORMATION
THERMAL CHARACTERISTICS
PARAMETER
R_θJA
Junction-to-free-air
thermal resistance
R_θJC
Junction-to-case
thermal resistance
TEST CONDITIONS
Board-mounted, no air flow, high conductivity TI recommended test
board, chip soldered or greased to thermal land
Board-mounted, no air flow, high conductivity TI recommended test
board with thermal land but no solder or grease thermal connection to
thermal land
Board-mounted, no air flow, JEDEC test board
Board-mounted, no air flow, high conductivity TI recommended test
board, chip soldered or greased to thermal land
Board-mounted, no air flow, high conductivity TI recommended test
board with thermal land but no solder or grease thermal connection to
thermal land
Board-mounted, no air flow, JEDEC test board
MIN TYP MAX UNIT
°C/W
°C/W
18
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