TLK2541 Datasheet, PDF (10/26 Pages) Texas Instruments – 1 TO 2.6 GBPS TRANSCEIVER

TLK2541
SLLS779B – JANUARY 2008 – REVISED APRIL 2008...................................................................................................................................................... www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
V_OD(p)
Preemphasis V_OD, direct,
V_OD(p) = |VTXP – VTXN|
R_t = 50Ω, PREM = high, dc-coupled, See
Figure 4
Rt = 50Ω, PREM = low, dc-coupled, See
Figure 4
V_{OD(pp_p)}
Differential peak-to-peak output voltage
with preemphasis
R_t = 50Ω, PREM = high, dc-coupled, See
Figure 4
Rt = 50Ω, PREM = low, dc-coupled, See
Figure 4
V_OD(d)
Deemphais output voltage,
|VTXP–VTXN|
R_t = 50Ω, dc-coupled, See Figure 4
V_{OD(pp_d)} Differential, peak-to-peak output
voltage with deemphasis
R_t = 50Ω, dc-coupled, See Figure 4
V_(cmt)
Transmit common mode voltage range,
(VTXP + VTXN)/2
R_t = 50Ω, See Figure 4
V_ID
Receiver input voltage differential,
|VRXP – VRXN|
V_(cmr)
Receiver common mode voltage range,
(VRXP + VRXN)/2
Ci Receiver input capacitance
Serial data total jitter (peak-to-peak)
Differential output jitter at 2.5 Gbps, Random
*12 + deterministic, Based on K28.5/K28.5
pattern
Differential output jitter at 1.25 Gbps,
Random*12 + deterministic, PRBS Pattern
Serial data total jitter (Random)
Random Jitter (RMS)
t_t, t_f
Differential output signal rise, fall time
(20% to 80%)
R_L = 50Ω, C_L = 5 pF, See Figure 4
Jitter tolerance, Total jitter at serial
input
Differential input jitter, random +
deterministic, PRBS pattern at zero crossing
at 1.25 Gbps
Jitter tolerance, Deterministic jitter at
serial input
Differential input jitter, deterministic, PRBS
pattern at zero crossing at 1.25 Gbps
Jitter tolerance, Total jitter at serial
input
Differential input jitter, random +
deterministic, PRBS pattern at zero crossing
at 2.5 Gbps
Jitter tolerance, Deterministic jitter at
serial input
Differential input jitter, deterministic, PRBS
pattern at zero crossing at 2.5 Gbps
t_{d(Tx latency)} Tx latency with Coding Off
Tx latency with Coding On
See Figure 6
t_{d(Rx latency)} Rx latency for Full Rate
Rx latency for Half Rate
See Figure 9
(1) UI is the time interval of one serialized bit.
MIN
750
700
1500
1400
500
1000
1000
200
1000
50
70
81
69
NOM
913
850
1825
1700
600
1300
1250
1250
150
MAX
1075
1000
UNIT
mV
2150
2000
mV_PP
800 mV
1600 mV_PP
1400 mV
1600 mV
2250 mV
2 pF
.32
0.19
.016
.75
UI ⁽¹⁾
UI
ps
UI
.462
UI
.60
UI
.37
UI
106
bits
126
100
bits
83
Figure 4. Differential and Common-Mode Output Voltage Definitions
10
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