TMS320DM6467_09 Datasheet, PDF (49/357 Pages) Texas Instruments – Digital Media System-on-Chip

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3.7.10 Host-Port Interface (HPI)
TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
Table 3-14. HPI Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
OTHER ^{(2) (3)}
DESCRIPTION
Host-Port Interface (HPI)
HPI is enabled by the PINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependent for 16-/32-bit modes). For more detailed information on
the HPI pin muxing, see Section 4.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_PERR/
HCS/
EM_DQM1
C3 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI active-low chip select input, HCS (I).
PCI_STOP/
HCNTL0/
EM_WE
D5 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI control input 0, HCNTL0 (I)
PCI_DEVSEL/
HCNTL1/
B3 I/O/Z
EM_BA[1]
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI control input 1, HCNTL1 (I).
PCI_PAR/HAS/
EM_DQM0
D4
I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI address strobe, HAS (I).
NOTE: The DM6467 HPI does not support the HAS feature. For proper HPI
operation if the pin is routed out, it must be pulled up via an external resistor.
PCI_SERR/
HDS1/EM_OE
B2
PCI_CBE2/
HDS2/EM_CS2
C4
PCI_CBE3/
HR/W/EM_CS3
A5
PCI_TRDY/
HHWIL/
E6
EM_A[16]/(ALE)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI data strobe input 1, HDS1 (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI data strobe input 2, HDS2 (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI host read/write select input, HR/W (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI half-word identification input control, HHWIL (I).
PCI_AD31/
DD15/
A8
HD31/EM_A[15]
PCI_AD30/
DD14/
C9
HD30/EM_A[14]
PCI_AD29/
DD13/
B8
HD29/EM_A[13]
PCI_AD28/
DD12/
D9
HD28/EM_A[12]
PCI_AD27/
DD11/
A6
HD27/EM_A[11]
I/O/Z
IPD
DV_DD33
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
In HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
PCI_AD26/
DD10/
C8
HD26/ EM_A[10]
PCI_AD25/
DD9/
B6
HD25/EM_A[9]
PCI_AD24/
DD8/
D8
HD24/EM_A[8]
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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