TMS320DM6467_09 Datasheet, PDF (189/357 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
This is the System Reset sequence:
1. The System Reset is initiated by the emulator.
During this time, the following happens:
– The reset signals flow to the entire chip resetting all the modules on chip, except the test and
emulation logic.
– The PLL Controllers are not reset. Internal system clocks are unaffected. If PLL1/PLL2 were locked
before the System Reset, they remain locked.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
– The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
– The clock and reset of each peripheral (except the DDR2 Memory Controller) is determined by the
default settings of the Power and Sleep Controller (PSC).
– The DDR2 Memory Controller registers retain their previous values. Only the DDR2 Memory
Controller state machines are reset by the System Reset.
– The PLL Controllers are operating in the mode prior to System Reset. The System clocks are
unaffected.
– The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a System Reset, the previous values (as shown in the BOOTCFG register) are used to select the
boot mode. For more details on the boot sequence, see the Using the TMS320DM646x Bootloader
Application Report (literature number SPRAAS0).
7.7.5 C64x+ Local Reset (DSP Local Reset)
With access to the PSC registers, the ARM can perform two types of DSP reset: DSP local reset and DSP
module reset. When DSP local reset is asserted, the DSP’s internal memories (L1P, L1D, and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of the DSP subsystem, as the DSP
module reset would. Local reset is useful when the DSP module is in the enable state or in the disable
state. The DSP module reset takes precedence over local reset. The ARM uses local reset to reset the
DSP to initiate the DSP boot process. The intent of module reset is to completely reset the DSP (like hard
reset). For more detailed information on DSP local reset and DSP module reset, see the ARM-DSP
Integration Chapter in the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
For information on peripheral selection at the rising edge of POR or RESET, see Section 4, Device
Configurations of this data manual.
7.7.6 Peripheral Local Reset
The user can configure the local reset and clock state of a peripheral through programming the PSC.
Table 7-3, DM6467 LPSC Assignments, identifies the LPSC numbers and the peripherals capable of
being locally reset by the PSC. For more detailed information on the programming of these peripherals by
the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
7.7.7 Reset Priority
If any of the above reset sources occur simultaneously, the PLLC only processes the highest-priority reset
request. The reset request priorities, from high to low, are as follows:
• Power-on Reset
• Maximum Reset
• Warm Reset
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Peripheral Information and Electrical Specifications 189