TMS320DM6467_09 Datasheet, PDF (36/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
3.7.5 Asynchronous External Memory Interface (EMIFA)
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Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions
SIGNAL
NAME
VP_DOUT4/
CS2BW
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
EMIFA BOOT CONFIGURATION
AA7 I/O/Z
IPD
DV_DD33
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus
width for the CS2 (boot) chip select region.
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
VP_DOUT6/
DSPBOOT
AC5 I/O/Z
IPD
DV_DD33
After reset, this pin is video port data output 4 (VP_DOUT4).
DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
The DSP is booted by the ARM when DSPBOOT = 0.
The DSP boots from EMIFA when DSPBOOT=1.
PCI_CBE2/
HDS2/
C4
EM_CS2
PCI_CBE3/
HR/W
A5
EM_CS3
PCI_GNT/
DACK/
D10
GP[12]/EM_CS4
PCI_REQ/
DMARQ/
B9
GP[11]/ EM_CS5
PCI_IDSEL/
HDDIR/
E8
EM_R/W
PCI_SERR/
HDS1/
B2
EM_OE
PCI_STOP/
HCNTL0/
D5
EM_WE
PCI_PERR/
HCS/
C3
EM_DQM1
PCI_PAR/
HAS/
D4
EM_DQM0
PCI_INTA/
EM_WAIT2/
C11
(RDY2/BSY2)
PCI_RSV5/IORDY/
GP[21]/EM_WAIT3/ D11
(RDY3/BSY3)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
After reset, this pin is video port data output 6 (VP_DOUT6).
EMIFA FUNCTIONAL PINS: ASYNC
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
memories (i.e., NOR Flash).
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is Chip Select 4 output EM_CS4 (O/Z). Asynchronous
memories (i.e., NOR Flash).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is Chip Select 5 output EM_CS5 (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, and EMIFA.
In EMIFA mode, this pin is the read/write output EM_R/W (O/Z).
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
These pins are multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, these pins are EM_DQM[1:0] and act as byte enables (O/Z).
This pin is multiplexed between PCI and EMIFA.
In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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