TMS320DM6467_09 Datasheet, PDF (186/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
www.ti.com
7.7 Reset
The reset controller detects the different type of resets supported on the DM6467 device and manages the
distribution of those resets throughout the device.
The DM6467 device has several types of device-level global resets—power-on reset, warm reset, max
reset, and system reset. Table 7-20 explains further the types of reset, the reset initiator, and the effects of
each reset on the chip. See Section 7.7.9, Reset Electrical Data/Timing, for more information on the
effects of each reset on the PLL controllers and their clocks.
TYPE
Power-on Reset
(POR)
Warm Reset
Max Reset
System Reset
C64x+ Local Reset
(DSP Reset)
Table 7-20. Device-Level Global Reset Types
POR pin
INITIATOR
RESET pin
Emulator, WD Timer (Timer 2)
Emulator
Software (register bit)
EFFECT(S)
Global chip reset (Cold reset). Activates the POR signal on chip,
which resets the entire chip including the emulation logic.
The power-on reset (POR) pin must be driven low during power
ramp of the device.
Device boot and configuration pins are latched.
Resets everything except for the emulation logic. Emulator stays
alive during Warm Reset.
Device boot and configuration pins are latched.
Same as a Warm Reset, except the DM6467 device boot and
configuration pins are not re-latched.
A system reset maintains memory contents and does not reset the
test and emulation circuitry. The device boot and configuration pins
are also not re-latched.
MMR controls the C64x+ reset input. This is used for control of
C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive
when in local reset.
In addition to device-level global resets, the PSC provides the capability to cause local resets to
peripherals and/or the C64x+ DSP.
7.7.1 Power-on Reset (POR Pin)
Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test
and emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes
through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power
supplies have reached their normal operating conditions. If an external 27-MHz oscillator is used on the
DEV_MXI/DEV_CLKIN pin, the source clock should also be running at the correct frequency prior to
de-asserting the POR pin. Note: A device power-up cycle is not required to initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset.
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
2. Wait for the input clock source to be stable while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted
(low) for a minimum of 12 DEV_MXI cycles.
Within the low period of the POR pin, the following happens:
– The reset signals flow to the entire chip (including the test and emulation logic), resetting the
modules on chip.
– The PLL Controller clocks start at the frequency of the DEV_MXI clock. The clocks are propagated
throughout the chip to reset the chip synchronously. By default, both PLL1 and PLL2 are in reset
and unlocked. The PLL Controllers default to PLL Bypass Mode.
4. The POR pin may now be deasserted (driven high).
186 Peripheral Information and Electrical Specifications
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