TMS320DM6467_09 Datasheet, PDF (223/357 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
7.11 Video Port Interface (VPIF)
The DM6467 Video Port Interface (VPIF) allows the capture and display of digital video streams. Features
include:
• 99-MHz VPIF (-594 Devices Only) and 108-MHz VPIF (-729 Devices Only)
• Up to 2 Video Capture Channels (Channel 0 and Channel 1)
– Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
– Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
– Single Raw Video (8-/10-/12-bit)
• Up to 2 Video Display Channels (Channel 2 and Channel 3)
– Two 8-bit SD Video Display with embedded timing codes (BT.656)
– Single 16-bit HD Video Display with embedded timing codes (BT.1120)
The VPIF capture channel input data format is selectable based on the settings of the specific Channel
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register. For more detailed information on these specific Channel Control
Registers, see the TMS320DM646x DMSoC Video Port Interface (VPIF) User's Guide (Literature Number
SPRUER9).
7.11.1 VPIF Bus Master Memory Map
The VPIF peripheral includes a bus master interface that accesses the DM6467 system bus to transfer
video-capture and video-display data. Table 7-45 shows the memory map for the VPIF master interface.
START
ADDRESS
0x0000 0000
0x8000 0000
0xA000 0000
0xC000 0000
Table 7-45. VPIF Master Memory Map
END
ADDRESS
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
SIZE
(BYTES)
2G
512M
512M
1G
VPIF MASTER INTERFACE
Reserved
DDR2 Memory Controller
Reserved
Reserved
7.11.2 VPIF Clock Control (Capture and Display)
The source clocks for the VPIF data channels are selectable based on the settings of the VIDCLKCTL
register (0x01C4 0038) (For the VIDCLKCTL register details, see Section 4.3.2.1, Video Clock Control
Register). The VSCLKDIS register (0x01C4 006C) is used to disable the clock inputs when changing the
clock source to ensure glitch-free operation. (For the VSCLKDIS register details, see Section 4.3.2.3,
Video and TSIF Clock Disable).
For both the VPIF dual 8-bit or 16-bit video-capture modes, Channel 0 is always clocked by VP_CLKIN0
(see Figure 7-35).
VP_CLKIN0
VP_CLKIN0
VPIF
Channel 0
Input Clock Source
VSCLKDIS.VID0
Figure 7-35. VPIF Capture Channel 0 Source Clock
Video-Capture Channel 1 is clocked by the VP_CLKIN1 signal, when the dual 8-bit capture mode is
enabled. When the 16-bit capture mode or 8-/10-/12-bit raw-capture mode is used, VP_CLKIN0 must be
selected as the clock source (VIDCLKCTL.VCH1CLK = 0) [see Figure 7-36].
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Peripheral Information and Electrical Specifications 223