TMS320DM6467_09 Datasheet, PDF (269/357 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
Table 7-86. Switching Characteristics for Host-Port Interface Cycles^(1)(2)(3)
(see Figure 7-59 through Figure 7-62)
NO.
PARAMETER
-594, -729
MIN
MAX
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full
or flushing (can be either first or
second half-word)
Case 4: HPIA write and Write FIFO not
empty
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
5
t_{d(HSTBL-HRDYV)}
Delay time, HSTROBE low to ^{Case 1: HPID read (with}
HRDY valid
auto-increment) and data not in Read
12
FIFO (can only happen to first
half-word of HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6
t_en(HSTBL-HD)
Enable time, HD driven from HSTROBE low
2
7
t_d(HRDYL-HDV)
Delay time, HRDY low to HD valid
0
8
t_{oh(HSTBH-HDV)}
Output hold time, HD valid after HSTROBE high
1.5
14
t_{dis(HSTBH-HDV)}
Disable time, HD high-impedance from HSTROBE high
12
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
15
t_d(HSTBL-HDV)
Delay time, HSTROBE low to
HD valid
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is
12
already in Read FIFO
Case 3: Second half-word of HPID
read with or without auto-increment
(1) M = SYSCLK3 period = (CPU clock frequency)/4 in ns. For example, when running parts at 594 MHz, use M = 1.68 ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
UNIT
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 269