TMS320DM6467_09 Datasheet, PDF (38/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
www.ti.com
Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
PCI_AD26/
DD10/
HD26/EM_A[10]
PCI_AD25/
DD9/
HD25/EM_A[9]
PCI_AD24/
DD8/
HD24/EM_A[8]
PCI_AD23/
DD7/
HD23/EM_A[7]
PCI_AD22/
DD6/
HD22/EM_A[6]
PCI_AD21/
DD5/
HD21/EM_A[5]
PCI_AD20/
DD4/
HD20/EM_A[4]
PCI_AD19/
DD3/
HD19/EM_A[3]
PCI_AD18/
DD2/
HD18/EM_A[2]
PCI_AD17/
DD1/
HD17/EM_A[1]
PCI_AD16/
DD0/
HD16/EM_A[0]
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
C8 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 10 output EM_A[10] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
B6 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 9 output EM_A[9] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
D8 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 8 output EM_A[8] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
B5 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 7 output EM_A[7] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C7 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 6 output EM_A[6] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C5 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 5 output EM_A[5] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
D7 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 4 output EM_A[4] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
A4 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 3 output EM_A[3] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
E7 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 2 output EM_A[2] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
B4 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 1 output EM_A[1] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C6 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 0 output EM_A[0] (O/Z), which is the least
significant bit on a 32-bit word address.
When connected to a 16-bit asynchronous memory, this pin is the second bit of
the address.
For an 8-bit asynchronous memory, this pin is the third bit of the address.
38
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