HPC3130A Datasheet, PDF (36/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
PCI timing requirements over recommended ranges of supply voltage and operating free–air
temperature^† (see Note 3)
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN MAX UNITS
tpd
Propagation delay time
PCLK to shared signal valid delay
time
CL = 50 pF,
tval
See Note 4,
1,2,3
2
11 ns
ten Enable time, high-impedance-to-active delay time from PCLK
ton
2
ns
tdis Disable time, active-to-high-impedance delay time from PCLK
toff
28 ns
tsu Valid setup time, before PCLK
tsu
3,4
3
ns
th
Hold time, after PCLK high
† _{Applies to external output buffers.}
th
4
0
ns
NOTES: 3. This data sheet uses the following conventions to describe time ( t ) intervals. The format is: tA, where subscript A indicates the type
of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time,
and th = hold time.
4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, PCIFRAME, PCITRDY, PCIIRDY, PCISTOP, IDSEL, PCIDEVSEL, and
PCIPAR.
serial bus interface^†
STANDARD
MODE
MIN MAX
FAST MODE
MIN MAX
UNIT
fSCL
tBUF
tHD;STA
SCL clock frequency (see Note 5)
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
0 100
4.7
4
0 400 kHz
1.3
µs
0.6
µs
tLOW
LOW period of the SCL clock
4.7
1.3
µs
tHIGH
HIGH period of the SCL clock
4
0.6
µs
tSU;STA Setup time for a repeated START condition
4.7
0.6
µs
tHD;DAT Data hold time (see Note 6)
For CBUS compatible masters:
5
For serial bus devices:
01
µs
01 0.92
tSU;DAT Data setup time (see Note 7)
250
1003
µs
tR
Rise time of both SDA and SCL signals
1000
20 300 µs
tF
Fall time of both SDA and SCL signals
300
20 300 µs
tFSU;STO Setup time for STOP condition
4
0.6
µs
† _{All values refer to serial bus interface VIH MIN and VIL MAX levels}
NOTES: 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH _MIN of the SCL signal) in order
to bridge the undefined region of the falling edge of SCL.
6. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW ) of the SDL signal.
7. A fast mode serial bus device can be used in a standard mode serial bus system, but the requirement tSU;DAT > 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR _MAX + tSU;DAT = 1000 + 250 = 1250 ns
(according to the Standard Mode Serial Bus Specification) before the SCL line is released.
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