HPC3130A Datasheet, PDF (28/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
hot-plug slot control register
Bit
7
Name
Type
R
Default
0
6
5
4
3
2
1
0
Hot-plug slot control register
R
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
1
0
1
Register:
Type:
Offset:
Default:
Description:
Hot-plug slot control
Read-only, Read/Write
02 (slot 0), 0Ah (slot 1), 12h (slot 2), 1Ah (slot 3)
2Dh
This register applies power, resets, and provides general control of a hot-plug slot
connection to the system PCI bus.
Table 10. Hot-Plug Slot Control Register
BIT TYPE
NAME
FUNCTION
7
R
RSVD
Reserved. This bit returns 0 when read.
6
R
RSVD
Reserved. This bit returns 0 when read.
Slot power On/Off control. The data written to this bit represents the logical value of the data to drive the
5
R/W
SLTPWR_CTL
PWRON/OFF output and is used to control the power state of a hot-plug slot. If the PROTECTEN bit in the
general configuration register is set to 1, then a logic high can only be driven by the PWRON/OFF output if
the DETECT[1:0] inputs are low.
PCI bus CBT-switch control. When manual sequencing is enabled, then the value written to this bit
represents the logical value of the data driven to the BUSON output, and it is used to connect/disconnect a
hot-plug slot to/from the PCI bus.
If an auto sequencing mode is enabled in the general configuration register, then this bit functions as follows:
4
R/W
BUS_CTL
1 = By setting this bit, the hot-plug slot gets disconnected from the PCI bus. This is accomplished by
asserting IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY
before driving BUSON high, CLKON high, REQ64ON low, and PWRON/OFF low.
0 = By clearing this bit, the hot-plug slot gets connected to the PCI bus. This is accomplished by asserting
IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY before driving
BUSON low. Also verifies assertion of DETECT[1:0] if the protection enable bit is enabled in the
general configuration register.
Slot request 64-bit control. The data written to this bit represents the logical value of the data driven to the
3
R/W SLOTREQ64 SLOTREQ64 output and is used during reset of a slot after power is applied. This input indicates to an option
card whether or not it is connected to a 64-bit slot.
2
R/W
REQ64_O
REQ64 CBT switch control. The data written to this bit represents the logical value of the data driven to the
REQ64ON output and is used to control the CBT switch that implements the REQ64 PCI signal.
CLKON CBT switch control. The data written to this bit represents the logical value of the data driven to the
1
R/W
CLKON_O _{CLKON output and is used to control the clock driver to the hot-plug slot.}
0
R/W
SLOTRST_O
Slot reset control. The data written to this bit represents the logical value of the data driven to the SLOTRST
output and is used to reset a hot-plug slot after power is applied.
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