HPC3130A Datasheet, PDF (13/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
Terminal Functions (Continued)
SCPS055 – NOVEMBER 1999
system interface
TERMINAL
NAME
NO. NO. NO. I/O
120 128 144
FUNCTION
FRAME
20
21
23
Frame. This input and the IRDY input indicate that the PCI bus is idle. When the HPC3130A
I senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot can be connected to the PCI
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
IDLEGNT
19
20
22
Idle grant. This input indicates when the PCI bus is idled by the HOST-PCI bridge after a
I request is made by IDLEREQ. The protocol is identical to PCI request/grant. This input must be
wired to a valid logic level if the bus idling procedure is not implemented.
IDLEREQ
Idle request. This output is driven to request the HOST-PCI bridge to idle the PCI bus before
18
19
21
O connecting a hot-plug slot. The protocol is identical to PCI request/grant. A pullup resistor must
be implemented on this terminal if the bus idling procedure is not implemented.
INTR
System interrupt. This output provides a system interrupt. The HPC3130A can be programmed
24
25
27
O
to assert this interrupt under various conditions, which may be serviced by the hot-plug service.
Furthermore, the event status/enable state is compliant with the ACPI Specification and, as a
result, supports ACPI control methods for switching the HPC3130A.
INTR
System interrupt. This open drain output provides a system interrupt. The HPC3130A can be
23
24
26
O
programmed to assert this interrupt under various conditions, which may be serviced by the
hot-plug. Furthermore, the event status/enable state is compliant with the ACPI Specification
and, as a result, supports ACPI control methods for switching the HPC3130A.
IRDY
21
22
24
Initiator ready. This and the FRAME input indicate that the PCI bus is idle. When the HPC3130A
I senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot may be connected to the PCI
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
PCLK
16
17
19
I
PCI clock input. These terminals provide the PCI clock to the HPC3130A, which uses it only for
activity indicator timing, IDLEREQ/IDLEGNT protocol, and connection sequencing.
PRST
14
15
17
PCI reset. This signal provides the PCI reset to the HPC3130A. After a PCI reset, the
I HPC3130A resides in a state where all slots are enabled, as in a non-hot-plug system. The
HPC3130A passes PCI resets from the host to all hot-plug slots.
SGNT
Secondary grant. This output provides a scheme to cascade a secondary HPC3130A device in
order to provide more than four slots. The SGNT output from the primary HPC3130A is input to
13
14
16
O
the IDLEGNT terminal for the secondary HPC3130A. After the secondary HPC3130A requests
the primary HPC3130A to idle the bus, the primary HPC3130A arbitrates for the bus using
IDLEREQ. Once IDLEGNT is asserted, the primary HPC3130A asserts its SGNT output. This
indicates to the secondary HPC3130A device that it can connect to the bus.
SMODE
27
28
30
Serial bus mode. When this input is asserted high, the internal HPC3130A registers are
I accessible through the serial bus interface; otherwise, they are accessed through the generic
parallel bus interface. This input selects the control bus interface.
SREQ
12
13
15
Secondary request. This input provides a scheme to cascade a second HPC3130A device in
order to provide more than four slots. The IDLEREQ from the second HPC3130A device is
I input to the SREQ terminal of the primary HPC3130A. If the second HPC3130A device
arbitrates for the bus by asserting its IDLEREQ output, this scheme causes the primary
HPC3130A to assert its IDLEREQ. If cascading is not used, this input is pulled high.
PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the
SYSM66EN 25
26
28 I/O hot-plug slots, and must be tied to the system PCI bus M66EN signal. The output from this
terminal only changes state after a PCI reset and is only required in a 66-MHz system.
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