HPC3130A Datasheet, PDF (12/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Terminal Functions
This section describes the HPC3130A terminal functions. The terminals are grouped in tables by function.
power supply terminal functions
NAME
GND
VCC
VCC5V
VCCP
TERMINAL
NO.
NO.
NO.
I/O
120
128
144
FUNCTION
11, 17, 26, 41, 51, 12, 18, 27, 44, 54, 14, 20, 29, 50, 60,
I Device ground terminals
68, 79, 101, 112, 117 73, 84, 108, 119, 124 83, 94, 122, 133, 138
6, 36, 56, 85, 95
7, 39, 59, 90, 102
9, 45, 65, 100, 116
I 3.3-V power supply
15, 28, 46, 74, 107 16, 29, 49, 79, 114 18, 32, 55, 89, 128
I 5-V clamp-rail voltage supply
22
23
25
I Clamp rail voltage for PCI signaling (5V or 3.3V)
control bus interface
TERMINAL
NAME
NO. NO. NO.
120 128 144
A2/ADD2
A1/ADD1
A0/ADD0
48 51 57
49 52 58
50 53 59
A4/ADD4
A3/ADD3
45 48 54
47 50 56
CS
34 37 43
DATA1/ADD6 43 46 52
DATA0/ADD5 44 47 53
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
35 38 44
37 40 46
38 41 47
39 42 48
40 43 49
42 45 51
RD/SDA
29 30 34
WR/SCL
30 31 36
I/O
FUNCTION
Parallel bus address. These terminals are address inputs in generic parallel bus cycles and are
only used when the SMODE is input low. These lower address terminals select one of the eight
I ^{registers for read/write access.}
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Parallel bus address. These terminals are address inputs in generic parallel bus cycles, and are
only used when SMODE is input low. These upper address terminals select one of four hot-plug
I ^{slots supported by the HPC3130A.}
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Chip selection. This active low input selects the HPC3130A chip as addressed in the current
I generic parallel bus cycle. This chip input is only valid if the SMODE is input low. Multiple
HPC3130A chips may exist in a system with external logic driving this signal.
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
I/O ^{registers when the parallel control bus interface is implemented.}
Serial bus address selection. These terminals indicate the full serial bus address of the
HPC3130A when the SMODE is input high.
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
I/O SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
Read selection. This terminal indicates a register read cycle when the SMODE input is low and
the CS terminal input is asserted. This is used to read an internal HPC3130A register.
I/O
Serial bus data. This terminal signals the serial bus data when the SMODE input is high. It is used
during internal register read and write transactions.
Write selection. This terminal indicates a register write cycle when the SMODE input is low and
the CS terminal input is asserted. This input is used to write to an internal HPC3130A register.
I
Serial bus clock. This terminal inputs serial bus clock in when the SMODE input is high. It is used
during internal register read and write transactions.
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