HPC3130A Datasheet, PDF (15/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
Terminal Functions (Continued)
SCPS055 – NOVEMBER 1999
slot control and status functions (continued)
TERMINAL
NAME
NO. NO. NO. I/O
120 128 144
FUNCTION
PWRON/OFF[3] 109 116 130
PWRON/OFF[2] 91
98 109
PWRON/OFF[1] 71
76
86
PWRON/OFF[0] 52
55
61
O
Power ON/OFF. This output is provided per slot and is driven to the power switch to control
the slot power state.
REQ64ON[3]
REQ64ON[2]
REQ64ON[1]
REQ64ON[0]
116 123 137
98 105 119
78
83
93
59
62
70
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
O
loading of the additional REQ64 signal inherent to the HPC3130A controller. This output
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
REQ64ON[3]
REQ64ON[2]
REQ64ON[1]
REQ64ON[0]
118 125 140
99 106 120
80
85
95
60
63
72
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
O
loading of the additional REQ64 signal inherent to the HPC3130A controller. This output
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
SLOTREQ64[3]
SLOTREQ64[2]
SLOTREQ64[1]
SLOTREQ64[0]
7
8
9
10
8
9
10
11
10
11
12
13
Slot request 64. This output is driven in conjunction with SLOTRST to the hot-plug slot to
indicate to option cards whether or not they are plugged into a 64-bit slot. If a 64-bit device
O is plugged into a 32-bit slot, then it must ensure that its high-word path inputs do not
oscillate and that there is not a significant power drain through the input buffer. This output
is only driven by the HPC3130A under programmed control.
SLOTRST[3]
SLOTRST[2]
SLOTRST[1]
SLOTRST[0]
115 122 136
97 104 118
77
82
92
58
61
68
Slot PCI reset. This output is driven to the hot-plug slot to reset it after power up. When a
O card is inserted into a hot-plug slot it must be reset independent of the other PCI devices on
the bus. This output is only driven by the HPC3130A under programmed control.
HPC3130A applications
This section discusses the various features of the HPC3130A in detail, and presents design considerations
including a general connection sequencing guideline.
system implementation
Figure 1 illustrates the HPC3130A implementation. The PCI bus signals are switched to the hot–plug PCI slot
by the BUSON output, which controls a CBT switch. The PCI clock, PCI reset, M66EN, and REQ64 must not
be routed through the CBT switch. The HPC3130A drives the slot PCI reset and SLOTREQ64, which can be
controlled by internal HPC3130A registers. The SLOTREQ64 requires special consideration during reset, as
described. The PCI clock to the slot is driven by a clock driver, which is enabled by the HPC3130A CLKON
output.
The HPC3130A also provides other features such as mechanical detection circuits, attention indicators, and
interrupt signaling. The mechanical detection circuitry using the DETECT[1,0] inputs is displayed as a dotted
line and is an optional feature. Two attention indicator outputs, ATTN[1,0], are provided: one indicator to draw
the attention of the user to a particular slot for insertion/removal, and one optional indicator that can be used
to indicate fault conditions. Additional features, such as 66-MHz capability and automatic sequencing, are
discussed in the following sections.
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