HPC3130A Datasheet, PDF (20/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
connection sequencing (continued)
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
IDLEGNT
FRAME
IRDY
BUSON
Figure 8. Automatic Connection Sequencing Mode 2
The protocol described above is identical to the PCI REQ/GNT protocol used by PCI bus masters, which also
must wait for bus idle through PCI FRAME and IRDY before initiating a PCI cycle. If the HPC3130A is connected
to PCI FRAME and IRDY, the HPC3130A arbitrates for the bus; although it does not drive the PCI bus or assert
FRAME to start a cycle.
There are some issues with this implementation such as bus parking and additional loading on the PCI FRAME
and IRDY signals, which need to be considered when designing a system. The system designer may have a
level of confidence that PCI adapter cards can tolerate connection to a non-idle bus. In the scenario where the
HPC3130A is not connected to the bus, then the FRAME, IRDY, and IDLEGNT must be wired to valid logic levels
and the automatic sequencing will start without any relationship to the bus.
20
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265