HPC3130A Datasheet, PDF (18/41 Pages) Texas Instruments – PCI HOT PLUG CONTROLLER

HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
master responds with an acknowledge signal, indicating that it requires additional data, the HPC3130A
continues to output data for each received acknowledge signal. The master terminates the sequential read
operation by not responding with an acknowledge signal, and issues a STOP condition.
Slave Address
Word Address
Slave Address
Data Byte
S b6 b5 b4 b3 b2 b1 b0 0 A b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 1 A b7 b6 b5 b4 b3 b2 b1 b0 M P
Start
R/W
A = Slave acknowledgment
Restart
M = Master acknowledgment
R/W
S/P = Start/stop condition
Stop
Figure 5. Serial Bus Protocol – Byte Read
parallel interface
The HPC3130A also implements an 8-bit parallel interface mode. When this mode is selected, the HPC3130A
internal register addressed by the A[4:0] inputs can be accessed for a read/write transaction using the CS, RD,
WR strobes. The following signals have pullups on the mother board: IO16, M16, NOWS, CHRDY, MEMR,
MEMW, IOR, IOW, SD[15:0] to implement default states. Figure 6 shows write access using the default 8-bit
standard ISA bus cycle with four wait states. A read cycle is similar.
BCLK
CS
WR
A(0–4)
D(0–7)
Figure 6. Parallel Bus Write Cycle
connection sequencing
Before an add-in card is hot plugged and made available to the slot, the various pins in the HPC3130A have
to be controlled in a specific sequence. The HPC3130A provides the software interface to sequence the power
to the slot, clocks, and signals to the add-in cards that are being live inserted. The switch-timing block is used
to control the exact timing when the CBT switches are enabled.
The initial software sequencing is done by setting individual bits in the hot plug control register in the following
sequence. First, the SLTPWR_CTL bit is set high to drive the PWRON/OFF signal high. After the power to the
slot is applied, the SLOTRST_O bit is set low to drive the SLOTRST output. Next the CLKON_O bit is set low
to enable the PCI clock to the slot. Also, the REQ64_O bit is set to a value of 0 and the SLOTREQ64 bit is set
to indicate to the add-in card whether it is inserted into a 64-bit or 32-bit slot. SLOTREQ64 is set low for a 64-bit
slot and is set high for a 32-bit slot.
After initial software sequencing of the above signals is complete, the next step is to enable the CBT switches.
This can be done either by using the software to manually set the BUS_CTL bit or using the HPC3130A via the
automatic connection sequence mode located in the general configuration register.
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