MSP430F2619S-HT Datasheet, PDF (26/90 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F2619S-HT
SLAS697B – MARCH 2010 – REVISED JUNE 2011
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Absolute Maximum Ratings⁽¹⁾
VALUE
UNIT
Voltage applied at V_CC to V_SS
Voltage applied to any pin⁽²⁾
Diode current at any device terminal
Storage temperature, T_stg (unprogrammed device⁽³⁾)
Storage temperature, T_stg (programmed device ⁽³⁾)
–0.3 to 4.1
V
–0.3 to V_CC + 0.3
V
±2
mA
–55 to 150
°C
–55 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions^{(1) (2)}
MIN NOM MAX UNIT
Supply voltage during program execution
V_{CC Supply voltage during flash memory}
AV_CC = DV_CC = V_CC ⁽³⁾
programming
1.8
3.6 V
2.2
3.6 V
V_SS Supply voltage
T_A Operating free-air temperature range
Processor frequency f_SYSTEM
(Maximum MCLK frequency)^{(1) (2)}
(see Figure 1)
AV_SS = DV_SS = V_SS
V_CC = 2.2 V, Duty Cycle = 50% ±10%
V_CC = 2.7 V, Duty Cycle = 50% ±10%
V_CC ≥ 3.3 V, Duty Cycle = 50% ±10%
0
V
–55
150 °C
dc
10
dc
12 MHz
dc
16
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
(3) It is recommended to power AV_CC and DV_CC from the same source. A maximum difference of 0.3 V between AV_CC and DV_CC can be
tolerated during power-up.
16 MHz
12 MHz
7.5 MHz
4.15 MHz
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Legend:
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
1.8 V 2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC
of 2.2 V.
Figure 1. Operating Area
26
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