MSP430F2619S-HT Datasheet, PDF (13/90 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F2619S-HT
www.ti.com
SLAS697B – MARCH 2010 – REVISED JUNE 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFF–0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed), the CPU goes
into LPM4 immediately after power up.
INTERRUPT SOURCE
Power up
External reset
Watchdog
Flash key violation
PC out-of-range⁽¹⁾
NMI
Oscillator fault
Flash memory access violation
Timer_B7
Timer_B7
Comparator_A+
Watchdog timer+
Timer_A3
Timer_A3
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
ADC12
I/O port P2 (eight flags)
I/O port P1 (eight flags)
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
DMA
DAC12
Reserved ^{(7) (8)}
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(2)
NMIIFG
OFIFG
ACCVIFG ^{(2) (3)}
TBCCR0 CCIFG⁽⁴⁾
TBCCR1 and TBCCR2
CCIFGs, TBIFG^{(2) (4)}
CAIFG
WDTIFG
TACCR0 CCIFG⁽⁴⁾
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG ^{(2) (4)}
UCA0RXIFG, UCB0RXIFG^{(2) (5)}
UCA0TXIFG, UCB0TXIFG⁽²⁾⁽⁶⁾
ADC12IFG ⁽⁴⁾
P2IFG.0 to P2IFG.7^{(2) (4)}
P1IFG.0 to P1IFG.7^{(2) (4)}
UCA1RXIFG, UCB1RXIFG^{(2) (5)}
UCA1TXIFG, UCB1TXIFG^{(2) (6)}
DMA0IFG, DMA1IFG,
DMA2IFG^{(2) (4)}
DAC12_0IFG, DAC12_1IFG⁽²⁾
(4)
Reserved
SYSTEM
INTERRUPT
Reset
(non)-maskable,
(non)-maskable,
(non)-maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
WORD ADDRESS
PRIORITY
0x0FFFE
31, highest
0x0FFFC
30
0x0FFFA
29
0x0FFF8
28
0x0FFF6
27
0x0FFF4
26
0x0FFF2
25
0x0FFF0
24
0x0FFEE
23
0x0FFEC
22
0x0FFEA
21
0x0FFE8
20
0x0FFE6
19
0x0FFE4
18
0x0FFE2
17
0x0FFE0
16
0x0FFDE
15
0x0FFDC
14
0x0FFDA to 0x0FFC0 13 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x00000 – 0x001FF)
or from within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) In SPI mode: UCB0RXIFG. In I²C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6) In UART/SPI mode: UCB0TXIFG. In I²C mode: UCB0RXIFG, UCB0TXIFG.
(7) The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY). A 0x0AA55 at this location disables the BSL completely. A
zero disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0x0FFDC to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
Copyright © 2010–2011, Texas Instruments Incorporated
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