OMAP-L137_15 Datasheet, PDF (197/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

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OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
6.28 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Supports ICEpick TAP Router power, clock and reset features. For details on ICEpick features see
http://tiexpressdsp.com/wiki/index.php?title=ICEPICK.
PSC0
BYTE ADDRESS
0x01C1 0000
0x01C1 0018
0x01C1 0040
0x01C1 0050
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01C1 0800 -
0x01C1 083C
0x01C1 0A00 -
0x01C1 0A3C
Table 6-103. Power and Sleep Controller (PSC) Registers
PSC1
BYTE ADDRESS
0x01E2 7000
0x01E2 7018
0x01E2 7040
0x01E2 7050
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
0x01E2 7800 -
0x01E2 787C
0x01E2 7A00 -
0x01E2 7A7C
ACRONYM
REVID
INTEVAL
MERRPR0
MERRCR0
PERRPR
PERRCR
PTCMD
PTSTAT
PDSTAT0
PDSTAT1
PDCTL0
PDCTL1
PDCFG0
PDCFG1
MDSTAT0-MDSTAT15
MDSTAT0-MDSTAT31
MDCTL0-MDCTL15
MDCTL0-MDCTL31
REGISTER DESCRIPTION
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
Module Status n Register (modules 0-15) (PSC0)
Module Status n Register (modules 0-31) (PSC1)
Module Control n Register (modules 0-15) (PSC0)
Module Control n Register (modules 0-31) (PSC1)
6.28.1 Power Domain and Module Topology
The SoC includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-104 and Table 6-105 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. The module states and terminology are defined in Section 6.28.1.2.
Copyright © 2008–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 197
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