OMAP-L137_15 Datasheet, PDF (113/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

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OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
BYTE ADRESS
0x01E2 0000 - 0x01E2 1FFF
Table 6-39. EMAC Control Module RAM
REGISTER DESCRIPTION
EMAC Local Buffer Descriptor Memory
No.
1 tc(REFCLK)
2 tw(REFCLKH)
3 tw(REFCLKL)
6 tsu(RXD-REFCLK)
7 th(REFCLK-RXD)
8 tsu(CRSDV-REFCLK)
9 th(REFCLK-CRSDV)
10 tsu(RXER-REFCLK)
11 th(REFCLKR-RXER)
Table 6-40. RMII Timing Requirements
PARAMETER
Cycle Time, RMII_MHZ_50_CLK
Pulse Width, RMII_MHZ_50_CLK High
Pulse Width, RMII_MHZ_50_CLK Low
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
MIN TYP MAX UNIT
20
ns
7
13 ns
7
13 ns
4
ns
2
ns
4
ns
2
ns
4
ns
2
ns
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter
tolerance of 50 ppm or less.
No.
4 td(REFCLK-TXD)
5 td(REFCLK-TXEN)
Table 6-41. RMII Switching Characteristics
PARAMETER
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
MIN TYP MAX UNIT
2.5
13 ns
2.5
13 ns
1
RMII_MHz_50_CLK
23
5
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
4
8
5
6
7
9
10
11
Figure 6-30. RMII Timing Diagram
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Peripheral Information and Electrical Specifications 113
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