OMAP-L137_15 Datasheet, PDF (138/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
www.ti.com
Table 6-64. General Timing Requirements for SPI1 Master Modes⁽¹⁾ (continued)
No.
5 t_{d(SPC_SIMO)M}
6 t_{oh(SPC_SIMO)M}
7 t_{su(SOMI_SPC)M}
8 t_{ih(SPC_SOMI)M}
PARAMATER
Delay, subsequent bits valid on
SPI1_SIMO after transmit edge of
SPI1_CLK
Output hold time, SPI1_SIMO valid
after
receive edge of SPI1_CLK
Input Setup Time, SPI1_SOMI valid
before
receive edge of SPI1_CLK
Input Hold Time, SPI1_SOMI valid
after
receive edge of SPI1_CLK
Polarity = 0, Phase =
0,
from SPI1_CLK rising
Polarity = 0, Phase =
1,
from SPI1_CLK falling
Polarity = 1, Phase =
0,
from SPI1_CLK falling
Polarity = 1, Phase =
1,
from SPI1_CLK rising
Polarity = 0, Phase =
0,
from SPI1_CLK falling
Polarity = 0, Phase =
1,
from SPI1_CLK rising
Polarity = 1, Phase =
0,
from SPI1_CLK rising
Polarity = 1, Phase =
1,
from SPI1_CLK falling
Polarity = 0, Phase =
0,
to SPI1_CLK falling
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Polarity = 1, Phase =
0,
to SPI1_CLK rising
Polarity = 1, Phase =
1,
to SPI1_CLK falling
Polarity = 0, Phase =
0,
from SPI1_CLK falling
Polarity = 0, Phase =
1,
from SPI1_CLK rising
Polarity = 1, Phase =
0,
from SPI1_CLK rising
Polarity = 1, Phase =
1,
from SPI1_CLK falling
MIN
MAX
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0
0
0
0
5
5
5
5
UNIT
5
5
ns
5
5
ns
ns
ns
No.
9
t_c(SPC)S
10 t_w(SPCH)S
11 t_w(SPCL)S
Table 6-65. General Timing Requirements for SPI1 Slave Modes⁽¹⁾
PARAMATER
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
MIN
greater of 3P or 40 ns
18
18
MAX
UNIT
ns
ns
ns
(1) P = SYSCLK2 period
138 Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: OMAP-L137
Copyright © 2008–2014, Texas Instruments Incorporated