OMAP-L137_15 Datasheet, PDF (132/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
www.ti.com
6.17.2 SPI Electrical Data/Timing
6.17.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-56 through Table 6-71 assume testing over recommended operating conditions (see Figure 6-38
through Figure 6-41).
Table 6-56. General Timing Requirements for SPI0 Master Modes⁽¹⁾
No.
1
t_c(SPC)M
2
t_w(SPCH)M
3
t_w(SPCL)M
4
t_{d(SIMO_SPC)M}
5
t_{d(SPC_SIMO)M}
6
t_{oh(SPC_SIMO)M}
7
t_{su(SOMI_SPC)M}
8
t_{ih(SPC_SOMI)M}
PARAMETER
Cycle Time, SPI0_CLK, All Master Modes
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Delay, initial data bit valid on
SPI0_SIMO after initial edge
on SPI0_CLK⁽²⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Delay, subsequent bits valid
on SPI0_SIMO after transmit
edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Output hold time, SPI0_SIMO
valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Input Setup Time, SPI0_SOMI
valid before
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Input Hold Time, SPI0_SOMI
valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
MIN
greater of 3P or 20
0.5t_c(SPC)M - 1
0.5t_c(SPC)M - 1
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0
0
0
0
5
5
5
5
MAX
256P
UNIT
ns
ns
ns
5
- 0.5t_c(SPC)M + 5
ns
5
- 0.5t_c(SPC)M + 5
5
5
ns
5
5
ns
ns
ns
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
132 Peripheral Information and Electrical Specifications
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