OMAP3530 Datasheet, PDF (180/230 Pages) Texas Instruments – Applications Processor

OMAP3530/25 Applications Processor
SPRS507 – FEBRUARY 2008
www.ti.com
Table 6-63. McSPI Interface Switching Requirements^(2)(4)(5)(6)
NO.
PARAMETER
SS6 t_{d(CLKAE-SOMIV)}
SS7 t_{d(CS0AE-SOMIV)}
Delay time, mcspix_clk active edge to mcspix_somi
shifted
Delay time, mcspix_cs0 active edge to Modes 0 and 2
mcspix_somi shifted
1.15 V
MIN
MAX
1.8
15.9
15.9
1.0 V
MIN
MAX
3.2
31.7
31.7
UNIT
ns
ns
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) The capacitive load is equivalent to 20 pF.
(3) P = mcspix_clk clock period
(4) In mcspix, x is equal to 1, 2, 3, or 4.
(5) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(6) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
Mode 0 & 2
mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
SS0
SS4
SS1
SS5
SS0
SS1
SS2
SS3
Bit n-1
SS7
Bit n-1
Bit n-2
SS6
Bit n-2
Bit n-3
Bit n-3
Bit n-4
Bit n-4
Bit 0
Bit 0
Mode 1 & 3
mcspix_cs0(EPOL=1)
SS0
SS1
mcspix_clk(POL=0)
SS0
SS4
SS1
SS5
mcspix_clk(POL=1)
SS3
SS2
mcspix_simo
Bit n-1 Bit n-2 Bit n-3
Bit 1
Bit 0
SS6
mcspix_somi
Bit n-1 Bit n-2 Bit n-3
Bit 1
Bit 0
030-076
Figure 6-35. McSPI Interface – Transmit and Receive in Slave Mode⁽¹⁾⁽²⁾
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.
180 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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