OMAP3530 Datasheet, PDF (115/230 Pages) Texas Instruments – Applications Processor

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OMAP3530/25 Applications Processor
SPRS507 – FEBRUARY 2008
4.2 Output Clock Specifications
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:
• sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be
controlled by software or externally using sys_clkreq control. When the device is in the off state, the
sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the
device. The off state polarity of sys_clkout1 is programmable.
• sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,
332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off
state polarity is programmable. This output is active only when the core domain is active.
Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.
Table 4-10. sys_clkout1 Output Clock Electrical Characteristics
NAME
f
C_I
DESCRIPTION
Frequency
Load capacitance⁽¹⁾
f(max) = 38.4 MHz
f(max) = 26 MHz
Amplitude of output clock
MIN
TYP
12, 13, 16.8, 19.2, 26, or 38.4
70
1.71
125
1.8⁽²⁾
(1) The load capacitance is adapted to a frequency.
(2) Voltage stress up to the maximum voltage values shown above operation at T_J of 25°C.
Table 4-11 details the sys_clkout1 output clock timing characteristics.
MAX
1.89
UNIT
MHz
pF
V
Table 4-11. sys_clkout1 Output Clock Switching Characteristics
NAME
f
CO1
1 / CO0
t_w(CLKOUT1)
DESCRIPTION
Frequency
Pulse duration, sys_clkout1 low or high
CO2
CO3
t_R(CLKOUT1)
t_F(CLKOUT1)
Rise time, sys_clkout1⁽¹⁾
Fall time, sys_clkout1⁽¹⁾
(1) With a load capacitance of 25 pF.
MIN
TYP
MAX
12, 13, 16.8, 19.2, 26, or 38.4
0.40 *
t_c(CLKOUT1)
0.60 *
t_c(CLKOUT1)
3.31
3.31
UNIT
MHz
ns
ns
ns
sys_clkout
CO0
CO1
Figure 4-7. sys_clkout1 System Output Clock
Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.
Table 4-12. sys_clkout2 Output Clock Electrical Characteristics
NAME
f
C_l
DESCRIPTION
Frequency
Load capacitance⁽¹⁾
Amplitude of output clock
f(max) = 166 MHz
f(max) = 96 MHz
f(max) = 65 MHz
MIN
1.71
TYP
8
20
25
1.8⁽²⁾
(1) The load capacitance is adapted to a frequency.
(2) Voltage stress up to the maximum voltage values shown above, operation at T_J = 25°C.
Table 4-13 details the sys_clkout2 output clock timing characteristics.
CO1
030-014
MAX
322
UNIT
MHz
pF
1.89
V
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CLOCK SPECIFICATIONS 115