OMAP3530 Datasheet, PDF (122/230 Pages) Texas Instruments – Applications Processor

OMAP3530/25 Applications Processor
SPRS507 – FEBRUARY 2008
www.ti.com
Table 4-19. DPLL3 Clock Frequency Ranges, VDD2 OPP1 (continued)
SDRC
GPMC
Clock Signal
Description
SDRC input clock, taken from CM L3_ICLK.
GPMC input clock, taken from CM L3_ICLK.
Config 1
(400 MHz)
Min
Max
-
41.5
-
41.5
Unit
MHz
MHz
Table 4-20 summarizes the DLL characteristics.
Table 4-20. DLL Characteristics
PARAMETER
Supply voltage vdds_dpll_dll
Junction operating temperature
Input clock frequency
Input load⁽²⁾
Lock time⁽³⁾
Relock time
(Mode transitions through idle mode)
MIN
NOM
1.71
1.8
–40
25
66
120
83
120
150
1
1
MAX
1.89
107
133
166
15
500
500
372
2
1.5
UNIT
V
°C
MHz
fF
Clocks
ns
Clocks
µs
µs
COMMENTS
APPLICATION MODE 0
APPLICATION MODE 1
IDLE to MODEMAXDELAY
IDLE to APPLICATION MODE 1 or 0
IDLE to APPLICATION MODE @133 MHz
IDLE to APPLICATION MODE @166 MHz
(1) May be lower due to SmartReflex operation.
(2) This parameter is design goal and is not tested on silicon.
(3) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off
after 3 µs.
122 CLOCK SPECIFICATIONS
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