OMAP3530 Datasheet, PDF (120/230 Pages) Texas Instruments – Applications Processor

OMAP3530/25 Applications Processor
SPRS507 – FEBRUARY 2008
Clock Signal
DPLL1:
CLKOUTX2
MPU_CLK
Table 4-15. DPLL1 Clock Frequency Ranges (continued)
Description
Max
OPP5
600
DPLL1 internal clock signal,
OPP4
550
generated through DPLL1
OPP3
500
Multiplier and Divider.
OPP2
500
OPP1
500
OPP5
600
OPP4
550
DPLL1 output clock, generated
from CLKOUT_M2X2.
OPP3
500
OPP2
250
OPP1
125
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Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4-16. DPLL2 Clock Frequency Ranges
Clock Signal
DPLL2_ALWON
_FCLK
DPLL2_FCLK
Description
DPLL2 reference clock input,
taken from PRM SYS_CLK.
DPLL2 high-frequency bypass
clock input, taken from CM
CORE_CLK.
DPLL2:
CLKOUTX2
DPLL2 internal clock signal,
generated through DPLL2
Multiplier and Divider.
DPLL2:
CLKOUT
DPLL2 internal clock signal,
generated by dividing DPLL2
CLKOUTX2 by 2.
IVA2_CLK
DPLL2 output clock, generated
from CLKOUT_M2.
OPP5
OPP4
OPP3
OPP2
OPP1
OPP5
OPP4
OPP3
OPP2
OPP1
OPP5
OPP4
OPP3
OPP2
OPP1
Max
TBD
TBD
860
800
720
720
720
430
400
360
360
360
430
400
360
180
90
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4-17 through Table 4-19 show the DPLL3 clock frequency ranges.
Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3
clock speed configuration.
Clock Signal
DPLL3_ALWON_FCLK
DPLL3: CLKOUTX2
DPLL3: CLKOUT
Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP3
Description
DPLL3 input reference clock, generated
by PRM.
DPLL3 internal clock signal, generated
through DPLL3 Multiplier and Divider.
DPLL3 internal clock signal, generated
by dividing DPLL3 CLKOUTX2 by 2.
Config 1
(166 MHz)
Min
Max
TBD TBD
50
664
25
332
Config 2
(133 MHz)
Min
Max
TBD TBD
50
532
25
266
Config 3
(100 MHz)
Min
Max
TBD TBD
50
400
25
200
Unit
MHz
MHz
MHz
120 CLOCK SPECIFICATIONS
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