AM1806 Datasheet, PDF (157/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658 – FEBRUARY 2010
Table 6-75. Additional ⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option ^{(2) (3)} (continued)
NO.
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
1.3V, 1.2V
MIN
MAX
0.5M+P+4
P+4
0.5M+P+4
P+4
P+15
P+15
1.1V
MIN
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
P+17
P+17
1.0V
MIN
MAX
0.5M+P+6
P+6
0.5M+P+6
P+6
P+19
P+19
UNIT
ns
ns
ns
Table 6-76. Additional⁽¹⁾ SPI1 Slave Timings, 5-Pin Option^{(2) (3)}
NO.
PARAMETER
1.3V, 1.2V
MIN
MAX
25 t_{d(SCSL_SPC)S}
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
P+1.5
0.5M+P+4
26 t_{d(SPC_SCSH)S}
Required delay from final SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
P+4
0.5M+P+4
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4
27 t_{ena(SCSL_SOMI)S} Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
28 t_{dis(SCSH_SOMI)S} Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
29 t_{ena(SCSL_ENA)S} Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid
P+15
P+15
15
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-70 ).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
1.1V
MIN
MAX
P+1.5
0.5M+P+5
P+5
0.5M+P+5
P+5
P+17
P+17
17
1.0V
MIN
MAX
P+1.5
0.5M+P+6
P+6
0.5M+P+6
P+6
P+19
P+19
19
UNIT
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 157