AM1806 Datasheet, PDF (139/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658 – FEBRUARY 2010
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
1
2
3
3
4
4
5
6
7
8
Bit(n1)
(n2)
(n3)
2
3
3
9
11
10
12
Bit 0
14
13 (A)
13 (A)
Bit(n1)
(n2)
(n3)
Figure 6-31. McBSP Timing^(B)
Table 6-58. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-32)
NO.
PARAMETER
1 t_su(FRH-CKSH) Setup time, FSR high before CLKS high
2 t_h(CKSH-FRH) Hold time, FSR high after CLKS high
1.3V, 1.2V
MIN MAX
4
4
1.1V
MIN MAX
4.5
4
1.0V
MIN MAX
5
4
UNIT
ns
ns
Table 6-59. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-32)
NO.
PARAMETER
1 t_su(FRH-CKSH) Setup time, FSR high before CLKS high
2 t_h(CKSH-FRH) Hold time, FSR high after CLKS high
1.3V, 1.2V
MIN MAX
5
4
1.1V
MIN MAX
5
4
1.0V
MIN MAX
10
4
UNIT
ns
ns
CLKS
FSR external
1
2
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 6-32. FSR Timing When GSYNC = 1
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Peripheral Information and Electrical Specifications 139
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