AM1806 Datasheet, PDF (148/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658 – FEBRUARY 2010
www.ti.com
Table 6-65. Additional SPI0 Master Timings, 5-Pin Option ^{(1) (2) (3)} (continued)
NO.
PARAMETER
22 t_{d(SCS_SPC)M}
Delay from SPI0_SCS active to first
SPI0_CLK ^{(7) (8) (9)}
23 t_{d(ENA_SPC)M}
Delay from assertion of SPI0_ENA
low to first SPI0_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.3V, 1.2V
MIN
MAX
2P-2
0.5M+2P-2
2P-2
0.5M+2P-2
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
MIN
2P-2
1.1V
MAX
0.5M+2P-2
2P-2
0.5M+2P-2
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
MIN
2P-3
1.0V
MAX
0.5M+2P-3
2P-3
0.5M+2P-3
3P+6
0.5M+3P+6
3P+6
0.5M+3P+6
UNIT
ns
ns
Table 6-66. Additional SPI0 Slave Timings, 4-Pin Enable Option ^{(1) (2) (3)}
NO.
PARAMETER
1.3V, 1.2V
MIN
MAX
1.1V
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5P-3
2.5P+17.5
1.5P-3
2.5P+20
Delay from final
24
t_{d(SPC_ENAH)S}
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
–
– 0.5M+1.5P-3 0.5M+2.5P+17. – 0.5M+1.5P-3
5
1.5P-3
2.5P+17.5
1.5P-3
–
0.5M+2.5P+20
2.5P+20
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5M+1.5P-3
–
0.5+2.5P+17.5
– 0.5M+1.5P-3
– 0.5+2.5P+20
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
1.0V
MIN
MAX
1.5P-3
2.5P+27
– 0.5M+1.5P-3
–
0.5M+2.5P+27
1.5P-3
2.5P+27
– 0.5M+1.5P-3 – 0.5+2.5P+27
UNIT
ns
148 Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Link(s): AM1806
Copyright © 2010, Texas Instruments Incorporated