AM1806 Datasheet, PDF (146/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658 – FEBRUARY 2010
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Table 6-63. Additional SPI0 Master Timings, 4-Pin Enable Option ^{(1) (2) (3)}
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5
3P+5
3P+6
17 t_{d(ENA_SPC)M}
Delay from slave assertion of SPI0_ENA active to first
SPI0_CLK from master.⁽⁴⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
0.5M+3P+5
3P+5
0.5M+3P+5
3P+5
0.5M+3P+6
ns
3P+6
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5
0.5M+3P+5
0.5M+3P+6
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+5
0.5M+P+5
0.5M+P+6
18 t_{d(SPC_ENA)M}
Max delay for slave to deassert SPI0_ENA after final SPI0_CLK
edge to ensure master does not begin the next transfer.⁽⁵⁾
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P+5
0.5M+P+5
P+5
0.5M+P+5
P+6
ns
0.5M+P+6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
P+5
P+6
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-61 ).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
NO.
19 t_{d(SCS_SPC)M}
Table 6-64. Additional SPI0 Master Timings, 4-Pin Chip Select Option ^{(1) (2) (3)}
PARAMETER
Delay from SPI0_SCS active to first SPI0_CLK^{(4) (5)}
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.3V, 1.2V
MIN
MAX
2P-1
1.1V
MIN
MAX
2P-2
0.5M+2P-1
0.5M+2P-2
2P-1
2P-2
0.5M+2P-1
0.5M+2P-2
1.0V
UNIT
MIN
MAX
2P-3
0.5M+2P-3
ns
2P-3
0.5M+2P-3
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-61 ).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
146 Peripheral Information and Electrical Specifications
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