71M6531D_10 Datasheet, PDF (79/120 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Name
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
EQU[2:0]
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
FIR_LEN[1:0]
FL_BANK[2:0]
Location Reset Wake Dir
Description
2008[2]
2008[3]
200F[3]
200F[2]
0
0 R/W Causes VARPULSE to be output on DIO7.
0
0 R/W Causes WPULSE to be output on DIO6.
0
0 R/W Causes XPULSE to be output on DIO8.
0
0 R/W Causes YPULSE to be output on DIO9.
SFR 9E
SFR 9F
0
0 R/W Serial EEPROM interface data.
0
0 R/W Serial EEPROM interface control.
Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
2005[5]
0
0 R/W
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
2000[7:5]
0
0 R/W Specifies the power equation to be used by the CE.
2002[0]
2002[1]
2007[4]
2007[5]
0
0 R/W _{Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-}
0
0
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
0
0
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9
0
0
Interrupts for details.
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls
the time taken for each conversion.
[M40MHZ, M26MHZ]
FIR_LEN[1:0]
Resulting FIR Resulting
Filter Cycles CK32 Cycles
Resulting
DC Gain
[00], [10], or [11]
00
138
1
0.110017
2007[3:2]
1
1 R/W
01
288
2
1.000
10
384
3
2.37037
[01]
00
186
1
0.113644
01
384
2
1.000
10
588
3
3.590363
SFR B6[2:0] 1
Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
1 R/W to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
v1.3
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