71M6531D_10 Datasheet, PDF (25/120 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Register
(Alternate Name)
ERASE
(FLSH_ERASE)
FL_BANK
PGADDR
(FLSH_PGADR[5:0])
FLSHCRL
IFLAGS
INTBITS
(INT0 … INT6)
SFR
Address
Bit Field
Name
R/W
Description
0x94
This register is used to initiate either the Flash
W Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
0xB6[2:0]
R/W Flash Bank Selection.
0xB7
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
R/W
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
0xB2[0] FLSH_PWE
Program Write Enable:
0: MOVX commands refer to XRAM
R/W
Space, normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
0xB2[1] FLSH_MEEN
Mass Erase Enable:
0: Mass Erase disabled (default).
W
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
0xB2[6] SECURE
Enables security provisions that prevent external
R/W
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be
set. Attempts to write zero are ignored.
0xB2[7] PREBOOT
R Indicates that the preboot sequence is active.
0xE8[0] IE_XFER
This flag monitors the XFER_BUSY interrupt.
R/W It is set by hardware and must be cleared by
the interrupt handler.
0xE8[1] IE_RTC
This flag monitors the RTC_1SEC interrupt. It
R/W is set by the hardware and must be cleared by
the interrupt handler.
0xE8[2] FWCOL1
R/W
This flag indicates that a flash write was in
progress while the CE was busy.
0xE8[3] FWCOL0
This flag indicates that a flash write was
R/W attempted when the CE was attempting to
begin a code pass.
0xE8[4] IE_PB
R/W
This flag indicates that the wake-up pushbutton
was pressed.
0xE8[5] IE_WAKE
R/W
This flag indicates that the MPU was awakened
by the autowake timer.
0xE8[6] PLL_RISE
R/W
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
0xE8[7] PLL_FALL
R/W
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
0xF8[6:0] INT6 … INT0
Interrupt inputs. The MPU may read these bits
R
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
0xF8[7] WD_RST
W The WDT is reset when a 1 is written to this
bit.
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be
cleared.
v1.3
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